【HDLbits--counter】

HDLbits--counter

在IC设计中，counter是十分普遍和重要的设计内容；

题目：基础计数器

verilog 复制代码

module top_module (
    input clk,
    input reset,
    output [9:0] q);
	
    always @(posedge clk) begin
        if(reset) begin
            q <= 0;
        end else begin
            if(q==999) begin
                q <= 0;
            end else begin
               q <= q + 1; 
            end
        end
    end
endmodule

题目：

verilog 复制代码

module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);
	
    always @(posedge clk) begin
        if(shift_ena) begin
            q <= {q[2:0],data};
        end else begin
           q <= q - 1'b1; 
        end
    end
endmodule

题目：

verilog 复制代码

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
	
    //============================
    //==Mearly FSM
    //============================
    parameter S0 = 3'b000;
    parameter S1 = 3'b001;
    parameter S2 = 3'b010;
    parameter S3 = 3'b100;
    
    reg[3 -1:0] cur_sta;
    reg[3 -1:0] nxt_sta;
    
    //==State transition
    always @(*) begin
        case(cur_sta)
            S0: nxt_sta = (data==1'b1) ? S1 : S0;
            S1: nxt_sta = (data==1'b1) ? S2 : S0;
            S2: nxt_sta = (data==1'b0) ? S3 : S2;
            S3: nxt_sta = S0;
            default: nxt_sta = S0;
        endcase
    end
    
    //==State D-flop-flop
    always @(posedge clk) begin
        if(reset) begin
            cur_sta <= S0;
        end else begin
           cur_sta <= nxt_sta; 
        end
    end
    
    //==Output 
    always @(posedge clk) begin
        if(reset) begin
            start_shifting <= 1'b0;
        end else begin
            start_shifting <= ((cur_sta==S3) && (data==1'b1)) ? 1 : start_shifting; 
        end
    end
endmodule