【HDLBits习题详解 2】Circuit - Sequential Logic（5）Finite State Machines 【更新中...】

1. Fsm1（Simple FSM 1 - asynchronous reset）

module top_module
#(
	parameter 	A = 0;
    parameter 	B = 1; 
),    
(
    output	reg	out,
    input 		clk,
    input 		areset,
    input 		in
);
    reg state, next_state;

    // Output logic
    // assign out = (state == ...);
    assign out = ;
    
    always @(*) begin
        // State transition logic
        case 
    end

    always @(posedge clk, posedge areset) begin
        if (areset == 1'b1) begin
            state		<= B;
            next_state	<= A;
        end else begin
            
        end
    end
endmodule