ILA
创建函数
proc create_my_ila {name widths} {
#----------------------------------------------------------
# Create IP
#----------------------------------------------------------
create_ip \
-name ila \
-vendor xilinx.com \
-library ip \
-module_name $name
#----------------------------------------------------------
# Probe Width
#----------------------------------------------------------
set n [llength $widths]
set cfg [list \
CONFIG.C_NUM_OF_PROBES $n \
]
for {set i 0} {$i < $n} {incr i} {
lappend cfg CONFIG.C_PROBE${i}_WIDTH [lindex $widths $i]
}
set_property -dict $cfg [get_ips $name]
#----------------------------------------------------------
# Generate Output Products
#----------------------------------------------------------
generate_target all [get_ips $name]
export_ip_user_files \
-of_objects [get_ips $name] \
-no_script \
-sync \
-force
#----------------------------------------------------------
# Create Synthesis Run
#----------------------------------------------------------
create_ip_run [get_ips $name]
launch_runs ${name}_synth_1
wait_on_run ${name}_synth_1
#----------------------------------------------------------
# Refresh Project
#----------------------------------------------------------
update_compile_order -fileset sources_1
puts ""
puts "======================================="
puts " ILA \"$name\" Generated Successfully!"
puts "======================================="
}
创建
create_my_ila ila_cpu {32 1 1 1}
例化
ila_cpu u_ila_cpu (
.clk (i_clk),
.probe0 (probe0_data), // 32bit
.probe1 (probe1_valid), // 1bit
.probe2 (probe2_state), // 1bit
.probe3 (probe3_addr) // 1bit
);
VIO
创建函数
proc create_my_vio {name in_widths out_widths} {
#----------------------------------------------------------
# Create IP
#----------------------------------------------------------
create_ip \
-name vio \
-vendor xilinx.com \
-library ip \
-module_name $name
#----------------------------------------------------------
# Probe Width
#----------------------------------------------------------
set in_num [llength $in_widths]
set out_num [llength $out_widths]
set cfg [list \
CONFIG.C_NUM_PROBE_IN $in_num \
CONFIG.C_NUM_PROBE_OUT $out_num \
]
# Input Probe Width
for {set i 0} {$i < $in_num} {incr i} {
lappend cfg CONFIG.C_PROBE_IN${i}_WIDTH [lindex $in_widths $i]
}
# Output Probe Width
for {set i 0} {$i < $out_num} {incr i} {
lappend cfg CONFIG.C_PROBE_OUT${i}_WIDTH [lindex $out_widths $i]
}
set_property -dict $cfg [get_ips $name]
#----------------------------------------------------------
# Generate Output Products
#----------------------------------------------------------
generate_target all [get_ips $name]
export_ip_user_files \
-of_objects [get_ips $name] \
-no_script \
-sync \
-force
#----------------------------------------------------------
# Create Synthesis Run
#----------------------------------------------------------
create_ip_run [get_ips $name]
launch_runs ${name}_synth_1
wait_on_run ${name}_synth_1
#----------------------------------------------------------
# Refresh Project
#----------------------------------------------------------
update_compile_order -fileset sources_1
puts ""
puts "======================================="
puts " VIO \"$name\" Generated Successfully!"
puts "======================================="
}
创建
create_my_vio vio_cpu {32 8 1} {1 1 16}
例化
vio_cpu u_vio_cpu (
.clk(i_clk),
//----------------------------
// Input
//----------------------------
.probe_in0 (cpu_pc),
.probe_in1 (cpu_state),
.probe_in2 (cpu_busy),
//----------------------------
// Output
//----------------------------
.probe_out0 (vio_rst),
.probe_out1 (vio_start),
.probe_out2 (vio_data)
);
Clock Wizard
创建函数
proc create_my_clk_wiz {name in_freq out_freqs} {
#----------------------------------------------------------
# Create IP
#----------------------------------------------------------
create_ip \
-name clk_wiz \
-vendor xilinx.com \
-library ip \
-module_name $name
#----------------------------------------------------------
# Configure Clock
#----------------------------------------------------------
set n [llength $out_freqs]
set cfg [list \
CONFIG.PRIM_IN_FREQ $in_freq \
CONFIG.NUM_OUT_CLKS $n \
CONFIG.RESET_TYPE {ACTIVE_LOW} \
CONFIG.USE_LOCKED {true} \
]
for {set i 0} {$i < $n} {incr i} {
set idx [expr {$i + 1}]
lappend cfg CONFIG.CLKOUT${idx}_REQUESTED_OUT_FREQ \
[lindex $out_freqs $i]
}
set_property -dict $cfg [get_ips $name]
#----------------------------------------------------------
# Generate Output Products
#----------------------------------------------------------
generate_target all [get_ips $name]
export_ip_user_files \
-of_objects [get_ips $name] \
-no_script \
-sync \
-force
#----------------------------------------------------------
# Create Synthesis Run
#----------------------------------------------------------
create_ip_run [get_ips $name]
launch_runs ${name}_synth_1
wait_on_run ${name}_synth_1
#----------------------------------------------------------
# Refresh Project
#----------------------------------------------------------
update_compile_order -fileset sources_1
puts ""
puts "======================================="
puts " Clock Wizard \"$name\" Generated Successfully!"
puts "======================================="
}
创建
create_my_clk_wiz clk_sys_100 50 {100}
例化
clk_sys_100 u_clk_sys (
.clk_in1 (i_clk),
.resetn (i_rst_n),
.clk_out1(clk100m),
.clk_out2(clk200m),
.clk_out3(clk25m),
.locked(w_locked)
);
BRAM
创建函数
proc create_my_bram {name depth width} {
#----------------------------------------------------------
# Create IP
#----------------------------------------------------------
create_ip \
-name blk_mem_gen \
-vendor xilinx.com \
-library ip \
-module_name $name
#----------------------------------------------------------
# Configure BRAM
#----------------------------------------------------------
set_property -dict [list \
CONFIG.Memory_Type {Single_Port_RAM} \
CONFIG.Write_Width_A $width \
CONFIG.Read_Width_A $width \
CONFIG.Write_Depth_A $depth \
CONFIG.Enable_A {Always_Enabled} \
CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
CONFIG.Use_Byte_Write_Enable {false} \
CONFIG.Load_Init_File {false} \
] [get_ips $name]
#----------------------------------------------------------
# Generate Output Products
#----------------------------------------------------------
generate_target all [get_ips $name]
export_ip_user_files \
-of_objects [get_ips $name] \
-no_script \
-sync \
-force
#----------------------------------------------------------
# Create Synthesis Run
#----------------------------------------------------------
create_ip_run [get_ips $name]
launch_runs ${name}_synth_1
wait_on_run ${name}_synth_1
#----------------------------------------------------------
# Refresh Project
#----------------------------------------------------------
update_compile_order -fileset sources_1
puts ""
puts "======================================="
puts " BRAM \"$name\" Generated Successfully!"
puts "======================================="
}
创建
create_my_bram bram_reg 1024 32
例化
bram_reg u_bram_reg (
.clka (i_clk),
.ena (1'b1),
.wea (i_we),
.addra (i_addr),
.dina (i_wdata),
.douta (o_rdata)
);
FIFO Generator
创建函数
proc create_my_fifo {name width depth} {
#----------------------------------------------------------
# Create IP
#----------------------------------------------------------
create_ip \
-name fifo_generator \
-vendor xilinx.com \
-library ip \
-module_name $name
#----------------------------------------------------------
# Configure FIFO
#----------------------------------------------------------
set_property -dict [list \
CONFIG.Fifo_Implementation {Common_Clock_Block_RAM} \
CONFIG.Input_Data_Width $width \
CONFIG.Input_Depth $depth \
CONFIG.Output_Data_Width $width \
CONFIG.Output_Depth $depth \
CONFIG.Reset_Type {Asynchronous_Reset} \
CONFIG.Performance_Options {First_Word_Fall_Through} \
] [get_ips $name]
#----------------------------------------------------------
# Generate Output Products
#----------------------------------------------------------
generate_target all [get_ips $name]
export_ip_user_files \
-of_objects [get_ips $name] \
-no_script \
-sync \
-force
#----------------------------------------------------------
# Create Synthesis Run
#----------------------------------------------------------
create_ip_run [get_ips $name]
launch_runs ${name}_synth_1
wait_on_run ${name}_synth_1
#----------------------------------------------------------
# Refresh Project
#----------------------------------------------------------
update_compile_order -fileset sources_1
puts ""
puts "======================================="
puts " FIFO \"$name\" Generated Successfully!"
puts "======================================="
}
创建
create_my_fifo fifo_uart 8 1024
例化
fifo_uart u_fifo_uart (
.clk (i_clk),
.rst (~i_rst_n),
.din (i_data),
.wr_en (i_wr),
.rd_en (i_rd),
.dout (o_data),
.full (o_full),
.empty (o_empty)
);