KPNP_PHY_SRAM_CONTROL[INST0]
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x11ce086c
Description: PHY external SRAM control register. Used by SMU/PSP to patch PHY FW.
Field Name | Bits | Default | Description |
---|---|---|---|
sram_bypass | 0 | 0x0 | 0: PHY lane FSM execute FW from SRAM; 1: PHY lane FSM execute FW from ROM |
sram_ext_ld_done | 1 | 0x0 | 0: PHY SRAM has not been loaded by external agent; 1: PHY SRAM has been loaded by external agent |
sram_init_done(Access: R) | 2 | 0x0 | 0: PHY SRAM has not been initialize with ROM values; 1: PHY SRAM has been initialize with ROM values |
KPNP_PHY_SRAM_CONTROL[INST1]
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x11de086c
Description: PHY external SRAM control register. Used by SMU/PSP to patch PHY FW.
Field Name | Bits | Default | Description |
---|---|---|---|
sram_bypass | 0 | 0x0 | 0: PHY lane FSM execute FW from SRAM; 1: PHY lane FSM execute FW from ROM |
sram_ext_ld_done | 1 | 0x0 | 0: PHY SRAM has not been loaded by external agent; 1: PHY SRAM has been loaded by external agent |
sram_init_done(Access: R) | 2 | 0x0 | 0: PHY SRAM has not been initialize with ROM values; 1: PHY SRAM has been initialize with ROM values |
PCS_GOPX1_PCS_WATCHDOG[INST0]
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x11cf0080
Description: Control registers RW.
Field Name | Bits | Default | Description |
---|---|---|---|
DetectTimeoutLimit | 7:0 | 0x20 | - |
ReadySerialTimeoutLimit | 15:8 | 0xFF | - |
RecoveryTimeoutLimit | 23:16 | 0xFF | - |
FcInitTimeoutLimit | 31:24 | 0xFF | - |
PCS_GOPX1_PCS_WATCHDOG[INST1]
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x11df0080
Description: Control registers RW.
Field Name | Bits | Default | Description |
---|---|---|---|
DetectTimeoutLimit | 7:0 | 0x20 | - |
ReadySerialTimeoutLimit | 15:8 | 0xFF | - |
RecoveryTimeoutLimit | 23:16 | 0xFF | - |
FcInitTimeoutLimit | 31:24 | 0xFF | - |
FUSE_DATA_1
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x5d004
Description: Fuse Data 1.
Field Name | Bits | Default | Description |
---|---|---|---|
DATA | 31:0 | 0x0 | Fuse Data |
FUSE_DATA_2
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x5d008
Description: Fuse Data 2.
Field Name | Bits | Default | Description |
---|---|---|---|
DATA | 31:0 | 0x0 | Fuse Data |
MP0_C2PMSG_0
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x3810500
Description: Inbound mailbox register (external->MP0). External access control by C2PMSG_ATTR_0. Reset by any Warm Reset event.
Field Name | Bits | Default | Description |
---|---|---|---|
CONTENT | 31:0 | 0x0 | message content |
MP0_C2PMSG_1
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x3810504
Description: Inbound mailbox register (external->MP0). External access control by C2PMSG_ATTR_0. Reset by any Warm Reset event.
Field Name | Bits | Default | Description |
---|---|---|---|
CONTENT | 31:0 | 0x0 | message content |
MP0_C2PMSG_20
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x3810550
Description: Inbound mailbox register (external->MP0). External access control by C2PMSG_ATTR_1. Reset by any Warm Reset event.
Field Name | Bits | Default | Description |
---|---|---|---|
CONTENT | 31:0 | 0x0 | message content |
MP0_C2PMSG_21
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x3810554
Description: Inbound mailbox register (external->MP0). External access control by C2PMSG_ATTR_1. Reset by any Warm Reset event.
Field Name | Bits | Default | Description |
---|---|---|---|
CONTENT | 31:0 | 0x0 | message content |
RSMU_COLD_RESETB_WAFLC
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x1042004
Description: Writing to this register can toggle cold_reset outputs from remote_smu to IP blocks.
Field Name | Bits | Default | Description |
---|---|---|---|
RSMU_COLD_RESETB | 0 | 0x0 | Cold reset assert with synced Cpl_PWROK, writing 0x1 will release cold reset to IP. |
RSMU_COLD_RESETB_WAFL_PCS[INST0]
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x1052004
Description: Writing to this register can toggle cold_reset outputs from remote_smu to IP blocks.
Field Name | Bits | Default | Description |
---|---|---|---|
RSMU_COLD_RESETB | 0 | 0x0 | Cold reset assert with synced Cpl_PWROK, writing 0x1 will release cold reset to IP. |
RSMU_COLD_RESETB_WAFL_PCS[INST1]
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: smn_addr_map:
0x1053004
Description: Writing to this register can toggle cold_reset outputs from remote_smu to IP blocks.
Field Name | Bits | Default | Description |
---|---|---|---|
RSMU_COLD_RESETB | 0 | 0x0 | Cold reset assert with synced Cpl_PWROK, writing 0x1 will release cold reset to IP. |
WAFL0: WAFL0_PCS_CONTROL
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: WaflcMmio:
0x4C0018
Description: Control bits for PCS.
Field Name | Bits | Default | Description |
---|---|---|---|
RSTB | 0 | 0x0 | active low reset to PCS |
CLK_READY | 1 | 0x0 | clock to PCS is stable |
LINK_STATE | 3:2 | 0x3 | change PCS LS state |
POWER_STATE | 5:4 | 0x0 |
WAFL1: WAFL1_PCS_CONTROL
- Access Type: [R/W]
- Bit Width: 32 bits
- Access Width: 8/16/32
- Address: WaflcMmio:
0x4D0018
Description: Control bits for PCS.
Field Name | Bits | Default | Description |
---|---|---|---|
RSTB | 0 | 0x0 | active low reset to PCS |
CLK_READY | 1 | 0x0 | clock to PCS is stable |
LINK_STATE | 3:2 | 0x3 | change PCS LS state |
POWER_STATE | 5:4 | 0x0 |
当然可以,我们来逐一解释每个部分:
-
KPNP_PHY_SRAM_CONTROL[INST0]
:- KPNP_PHY_SRAM_CONTROL: 这是一个控制寄存器的名字,通常是用于控制或配置某种功能或硬件模块。
- [INST0]: 表示这是这个控制寄存器的一个实例或版本,这可能意味着有多个相似的寄存器用于不同的目的或不同的硬件实例。
-
[R/W]: 表示这个寄存器是可读可写的。
-
32 bits: 这是寄存器的大小,表示这个寄存器由32位组成。
-
Access: 8/16/32: 这意味着可以使用8位、16位或32位访问该寄存器。
-
smn_addr_map:0x11ce086c : 这表示寄存器的地址是
0x11ce086c
。 -
DESCRIPTION: PHY external SRAM control register. Used by SMU/PSP to patch PHY FW:
- PHY: 这通常是物理层的缩写,是计算机网络的底层。
- external SRAM: 这是一种存储器,SRAM表示静态随机访问存储器。
- control register: 控制寄存器通常用于控制或配置硬件模块。
- SMU/PSP: 这些是特定的控制单元或处理器。具体的定义和功能取决于上下文,但在许多系统中,SMU可能表示系统管理单元,而PSP可能表示平台安全处理器。
- patch PHY FW: 这表示该寄存器被用来应用(或打)补丁到物理层的固件。
-
Field Name | Bits | Default | Description: 这是一个表格的头,描述了寄存器内部各个字段的名称、位位置、默认值以及描述。
-
sram_bypass:
- Bit: 0, 表示这是寄存器的第0位。
- Default: 0x0, 表示默认值为0。
- Description: 如果这一位为0,物理层的有限状态机(FSM)从SRAM执行固件; 如果为1,它从ROM执行固件。
-
sram_ext_ld_done:
- Bit: 1, 表示这是寄存器的第1位。
- Default: 0x0, 表示默认值为0。
- Description: 如果这一位为0,意味着物理层的SRAM尚未由外部代理加载; 如果为1,物理层的SRAM已由外部代理加载。
-
sram_init_done(Access: R):
- Bit: 2, 表示这是寄存器的第2位。
- Access: R: 这意味着这一位是只读的。
- Default: 0x0, 表示默认值为0。
- Description: 如果这一位为0,物理层的SRAM尚未使用ROM值进行初始化; 如果为1,它已经使用ROM值进行了初始化。
-
希望这可以帮助您更好地理解这个描述!