ARMv8系统寄存器-0

子羽潇潇2024-03-18 16:39

- System registers

In AArch64, system configuration is controlled through system registers, and accessed using MSR and MRS instructions. This contrasts with ARMv7-A, where such registers were typically accessed through coprocessor 15 (CP15) operations. The name of a register tells you the lowest

Exception level that it can be accessed from.

For example:

TTBR0_EL1 is accessible from EL1, EL2, and EL3.
TTBR0_EL2 is accessible from EL2 and EL3.

Registers that have the suffix _ELn have a separate, banked copy in some or all of the levels,though usually not EL0. Few system registers are accessible from EL0, although the Cache Type Register (CTR_EL0) is an example of one that can be accessible.

Code to access system registers takes the following form:

复制代码

	MRS x0, TTBR0_EL1 // Move TTBR0_EL1 into x0
	MSR TTBR0_EL1, x0 // Move x0 into TTBR0_EL1

Previous versions of the ARM architecture have used coprocessors for system configuration.However, AArch64 does not include support for coprocessors. Table 4-5 lists only the system registers mentioned in this book.

For a complete list, see Appendix J of the ARM Architecture Reference Manual - ARMv8, for ARMv8-A architecture profile.

The table shows the Exception levels that have separate copies of each register. For example,separate Auxiliary Control Registers (ACTLRs) exist as ACTLR_EL1, ACTLR_EL2 and ACTLR_EL3.