Floating-point Convert to Signed integer, rounding toward Zero (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.
浮点转换为带符号整数，四舍五入为零（标量）。此指令使用向零舍入模式将SIMD&FP源寄存器中的浮点值转换为32位或64位有符号整数，并将结果写入通用目标寄存器。
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated.
此指令可以生成浮点异常。根据FPCR中的设置，异常会导致在FPSR中设置标志，或生成同步异常。
Half-precision to 32-bit variant
Applies when sf == 0 && type == 11.
FCVTZS <Wd>, <Hn>
Half-precision to 64-bit variant
Applies when sf == 1 && type == 11.
FCVTZS <Xd>, <Hn>
Single-precision to 32-bit variant
Applies when sf == 0 && type == 00.
FCVTZS <Wd>, <Sn>
Single-precision to 64-bit variant
Applies when sf == 1 && type == 00.
FCVTZS <Xd>, <Sn>
Double-precision to 32-bit variant
Applies when sf == 0 && type == 01.
FCVTZS <Wd>, <Dn>
Double-precision to 64-bit variant
Applies when sf == 1 && type == 01.
FCVTZS <Xd>, <Dn>
403dc8: b94012c0 ldr w0, x22, #16
403dcc: 910042c1 add x1, x22, #0x10 // x1=0x43c288 + 0x10
403dd0: 34000100 cbz w0, 403df0 <ferror@plt+0x1f10>
403dd4: fd405660 ldr d0, x19, #168 // d0=4412.67
403dd8: 1e780002 fcvtzs w2, d0 // w2=4412
=> 0x0000000000403dd4: 60 56 40 fd ldr d0, x19, #168
(gdb) x/x $x19+168
0x449588: 0x851eb852
=> 0x0000000000403dd8: 02 00 78 1e fcvtzs w2, d0
(gdb) p/f $d0
$7 = {f = 4412.6700000000001, u = 4412.6700000000001, s = 4412.6700000000001}
(gdb) p/d $w2
$8 = 4412