目录
[0 前言](#0 前言)
[1 设计目标](#1 设计目标)
[2 Decoder1_2](#2 Decoder1_2)
[3 Decoder2_4](#3 Decoder2_4)
[4 6TSRAM](#4 6TSRAM)
[5 Precharge](#5 Precharge)
[6 Read_bit](#6 Read_bit)
[7 WR_bit](#7 WR_bit)
[8 one_bit](#8 one_bit)
[9 模块扩展性展示](#9 模块扩展性展示)
0 前言
记录一下来到skd上的强度比较大的一门课，数字集成电路2的lab设计还是蛮好的，该帖非详细教程只是单纯的写一些思虑并用作笔记，新手小白欢迎交流，有错勿喷！
1 设计目标
本篇的设计目标就是设计一个SRAM，SRAM主要包括6TSRAM的cell、precharge模块、读写模块以及decoder来进行地址选取，这里展示部分模块设计，同时SRAM的存储单元需要大规模的绘制，所以可复制延申也是设计的重要一环，接下来也会有具体的扩展展示，对1bit的存储单元进行存取仿真。
2 Decoder1_2
2.1symbol
2.2 schematic
2.3 layout
3 Decoder2_4
3.1symbol
3.2 schematic
3.3 layout
4 6TSRAM
4.1symbol
4.2 schematic
4.3 layout
5 Precharge
5.1symbol
5.2 schematic
5.3 layout
6 Read_bit
6.1symbol
6.2 schematic
6.3 layout
7 WR_bit
7.1symbol
7.2 schematic
7.3 layout
8 one_bit
8.1symbol
8.2 schematic
8.3 layout
8.4 hspice simulation
bash
*one_bit
.TEMP 25
.OPTIONS ACCURATE
.OPTIONS POST=2
.GLOBAL vdd! net14 net13 write_bit net16 net17 net18
* YOU SHOULD INCLUDE MODLE FILES
*.INCLUDE *'/NMOS_VTL.inc'
*.INCLUDE *'/PMOS_VTL.inc'
* YOU SHOULD INCLUDE YOUR NELIST
*.INCLUDE halfadder.sp
* YOU SHOULD ADD LOAD CAPACITANCE
* YOU SHOULD GIVE INPUT PATTERNS FOR TEST CASES
* YOU SHOULD GIVE PROPER INPUT PATTERNS FOR MAXIMUM DELAY
.PARAM PERIOD =160US
.PARAM T0= 0.1NS
.PARAM T1= T0+PERIOD
.PARAM T2= T1+0.1NS
.PARAM STEP= 1PS
VDD VDD! 0 0.7
VGND GND! 0 0
.TRAN STEP T2
* YOU SHOULD INCLUDE MODEL FILES
.INCLUDE "/home/centos/PDK/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/NMOS_VTL.inc"
.INCLUDE "/home/centos/PDK/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/PMOS_VTL.inc"
** Library name: myprojlab
** Cell name: 6TSRAM
** View name: schematic
.subckt myprojlab_6TSRAM_schematic bl blbar wl
m3 bl wl net10 0 NMOS_VTL L=50e-9 W=180e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m2 net8 wl blbar 0 NMOS_VTL L=50e-9 W=180e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m1 net10 net8 0 0 NMOS_VTL L=50e-9 W=270e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m0 net8 net10 0 0 NMOS_VTL L=50e-9 W=270e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m5 net10 net8 vdd! vdd! PMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m4 net8 net10 vdd! vdd! PMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
.ends myprojlab_6TSRAM_schematic
** End of subcircuit definition.
** Library name: myprojlab
** Cell name: Precharge
** View name: schematic
.subckt Precharge bl blbar precharge
m5 blbar precharge bl vdd! PMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m4 vdd! precharge bl vdd! PMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m3 vdd! precharge blbar vdd! PMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
.ends Precharge
** End of subcircuit definition.
** Library name: myprojlab
** Cell name: INV
** View name: schematic
.subckt INV in out
m0 out in 0 0 NMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m1 out in vdd! vdd! PMOS_VTL L=50e-9 W=180e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
.ends INV
** End of subcircuit definition.
** Library name: myprojlab
** Cell name: Write_bit
** View name: schematic
.subckt Write_bit bl blbar wen write_bit
m1 bl wen net17 0 NMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m0 net16 wen blbar 0 NMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
xi5 write_bit net08 INV
xi0 write_bit net16 INV
xi4 net08 net17 INV
.ends Write_bit
** End of subcircuit definition.
** Library name: myprojlab
** Cell name: Read_bit
** View name: schematic
.subckt Read_bit bl blbar ren read_bit
m1 bl ren net06 0 NMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m2 blbar ren net07 0 NMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
xi6 net07 net06 INV
xi5 net06 net10 INV
xi1 net10 read_bit INV
.ends Read_bit
** End of subcircuit definition.
** Library name: myprojlab
** Cell name: one_bit
** View name: schematic
.subckt one_bit rbit ren wbit wen wl precharge
xi0 net14 net13 wl myprojlab_6TSRAM_schematic
xi1 net14 net13 precharge Precharge
xi2 net14 net13 wen wbit Write_bit
xi3 net14 net13 ren rbit Read_bit
.ends one_bit
** End of subcircuit definition.
xi0 rbit ren wbit wen wl precharge one_bit
*Vin1 en gnd PULSE 0v 0.7v 159.9n 0.1n 0.1n 159.9n 320n
*Vin2 in4 gnd PULSE 0v 0.7v 79.9n 0.1n 0.1n 79.9n 160n
*Vin3 in3 gnd PULSE 0v 0.7v 39.9n 0.1n 0.1n 39.9n 80n
*Vin4 in2 gnd PULSE 0v 0.7v 19.9n 0.1n 0.1n 19.9n 40n
*Vin5 in1 gnd PULSE 0v 0.7v 9.9n 0.1n 0.1n 9.9n 20n
*Vin6 in0 gnd PULSE 0v 0.7v 4.9n 0.1n 0.1n 4.9n 10n
Vin2 precharge gnd PULSE 0v 0.7v 5u 0 0 35u 40u
Vin1 wl gnd PULSE 0v 0.7v 4u 0 0 36u 40u
Vin4 wen gnd PWL 2.999u 0v,3u 0.7v,40u 0.7v,40.001u 0v,80u 0v,82.999u 0v,83u 0.7v,120u 0.7v,120.001u 0v,160u 0v
Vin5 ren gnd PWL 42.999u 0v,43u 0.7v,80u 0.7v,80.001u 0v,122.999u 0v,123u 0.7v,160u 0.7v,160.001u 0v,
Vin3 wbit gnd PULSE 0v 0.7v 80u 0 0 80u 160u
.probe v(precharge) v(wl) v(wen) v(ren) v(wbit) v(rbit)
.probe v(net13) v(net14)
.probe v(write_bit) v(net16)
.probe v(write_bit) v(net16)
.END8.5 sim wave
9 模块扩展性展示
通过设计尺寸，SRAM阵列部分可以不通过连接其他的金属线实现彼此之间的连接，拓展性非常好
