ARM--按键/中断

按键

初始化

key.c

复用功能配置

IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B: 低四位（0101）

IOMUXC_SetPinMux(IOMUXC_UART1_CTS_B_GPIO1_IO18, 0);

SION(信号监控)1: 0 //0 DISABLED --- Input Path is determined by functionality

MUX_MODE(复用功能)4：0101 // ALT5 -- Select mux mode： ALT5 mux port：GPIO1_IO03 of instance：gpio1

电器特性配置

IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B

IOMUXC_SetPinConfig(IOMUXC_UART1_CTS_B_GPIO1_IO18, 0xF0B1);

HYS(压摆率)1: 0 //0 HYS_0_Hysteresis_Disabled; 输入不开启

PUS(上拉或者下拉)2: 11 // PUS_3_22K_Ohm_Pull_Up --- 22K Ohm Pull Up

PUE(拉与保持选择)1: 1 //选择拉

PKE(拉或保持使能)1: 1 //使能

ODE(漏极开漏)1: 0 //使能

SPEED(速度)2： 10 //SPEED_2_medium_100MHz_ --- medium(100MHz)

DSE(驱动能力)3: 000 //DSE_0_output_driver_disabled_ --- output driver disabled; 输出是才有用，所以关闭

SRE()0: 0 //SRE_0_Slow_Slew_Rate --- Slow Slew Rate

引脚方向

Chapter 28：General Purpose Input/Output (GPIO)

GPIOx_GDIR

GPIO1->GDIR &= ~(1 << 18);

0 INPUT --- GPIO is configured as input.

1 OUTPUT --- GPIO is configured as output.

开关检测

GPIOx_DR：开关断开高电平，开关按下低电平

中断

GIC介绍

通用目的的中断控制器（Generic Inierrupt Controller）

硬件 -> GIC -> 处理器

中断源 -> 中断控制器GIC -> 中断处理器内核kernal

GIC不同的版本

GIC V1：CortexA5
GIC V2: 32位处理器（CortexA7）
GIC V3 - V4：64位处理器（CortexA53 手机芯片）
GIC V5：重新架构数百核处理器（算力要求高的芯片服务器）

GIC内核

中断源：0-15 SGI（软终端）：软件产生的中断

16-31 PPI （私有外设中断）核间通信，内核与内核之间中断

32-1019 SPI（共享外设中断）外设所产生的中断

中断配置

外设终端

复制代码

typedef struct
{
        uint32_t RESERVED0[1024];
  __IOM uint32_t D_CTLR;                 /*!< Offset: 0x1000 (R/W) Distributor Control Register */
  __IM  uint32_t D_TYPER;                /*!< Offset: 0x1004 (R/ )  Interrupt Controller Type Register */
  __IM  uint32_t D_IIDR;                 /*!< Offset: 0x1008 (R/ )  Distributor Implementer Identification Register */
        uint32_t RESERVED1[29];
  __IOM uint32_t D_IGROUPR[16];          /*!< Offset: 0x1080 - 0x0BC (R/W) Interrupt Group Registers */
        uint32_t RESERVED2[16];
  __IOM uint32_t D_ISENABLER[16];        /*!< Offset: 0x1100 - 0x13C (R/W) Interrupt Set-Enable Registers */
        uint32_t RESERVED3[16];
  __IOM uint32_t D_ICENABLER[16];        /*!< Offset: 0x1180 - 0x1BC (R/W) Interrupt Clear-Enable Registers */
        uint32_t RESERVED4[16];
  __IOM uint32_t D_ISPENDR[16];          /*!< Offset: 0x1200 - 0x23C (R/W) Interrupt Set-Pending Registers */
        uint32_t RESERVED5[16];
  __IOM uint32_t D_ICPENDR[16];          /*!< Offset: 0x1280 - 0x2BC (R/W) Interrupt Clear-Pending Registers */
        uint32_t RESERVED6[16];
  __IOM uint32_t D_ISACTIVER[16];        /*!< Offset: 0x1300 - 0x33C (R/W) Interrupt Set-Active Registers */
        uint32_t RESERVED7[16];
  __IOM uint32_t D_ICACTIVER[16];        /*!< Offset: 0x1380 - 0x3BC (R/W) Interrupt Clear-Active Registers */
        uint32_t RESERVED8[16];
  __IOM uint8_t  D_IPRIORITYR[512];      /*!< Offset: 0x1400 - 0x5FC (R/W) Interrupt Priority Registers */
        uint32_t RESERVED9[128];
  __IOM uint8_t  D_ITARGETSR[512];       /*!< Offset: 0x1800 - 0x9FC (R/W) Interrupt Targets Registers */
        uint32_t RESERVED10[128];
  __IOM uint32_t D_ICFGR[32];            /*!< Offset: 0x1C00 - 0xC7C (R/W) Interrupt configuration registers */
        uint32_t RESERVED11[32];
  __IM  uint32_t D_PPISR;                /*!< Offset: 0x1D00 (R/ ) Private Peripheral Interrupt Status Register */
  __IM  uint32_t D_SPISR[15];            /*!< Offset: 0x1D04 - 0xD3C (R/ ) Shared Peripheral Interrupt Status Registers */
        uint32_t RESERVED12[112];
  __OM  uint32_t D_SGIR;                 /*!< Offset: 0x1F00 ( /W) Software Generated Interrupt Register */
        uint32_t RESERVED13[3];
  __IOM uint8_t  D_CPENDSGIR[16];        /*!< Offset: 0x1F10 - 0xF1C (R/W) SGI Clear-Pending Registers */
  __IOM uint8_t  D_SPENDSGIR[16];        /*!< Offset: 0x1F20 - 0xF2C (R/W) SGI Set-Pending Registers */
        uint32_t RESERVED14[40];
  __IM  uint32_t D_PIDR4;                /*!< Offset: 0x1FD0 (R/ ) Peripheral ID4 Register */
  __IM  uint32_t D_PIDR5;                /*!< Offset: 0x1FD4 (R/ ) Peripheral ID5 Register */
  __IM  uint32_t D_PIDR6;                /*!< Offset: 0x1FD8 (R/ ) Peripheral ID6 Register */
  __IM  uint32_t D_PIDR7;                /*!< Offset: 0x1FDC (R/ ) Peripheral ID7 Register */
  __IM  uint32_t D_PIDR0;                /*!< Offset: 0x1FE0 (R/ ) Peripheral ID0 Register */
  __IM  uint32_t D_PIDR1;                /*!< Offset: 0x1FE4 (R/ ) Peripheral ID1 Register */
  __IM  uint32_t D_PIDR2;                /*!< Offset: 0x1FE8 (R/ ) Peripheral ID2 Register */
  __IM  uint32_t D_PIDR3;                /*!< Offset: 0x1FEC (R/ ) Peripheral ID3 Register */
  __IM  uint32_t D_CIDR0;                /*!< Offset: 0x1FF0 (R/ ) Component ID0 Register */
  __IM  uint32_t D_CIDR1;                /*!< Offset: 0x1FF4 (R/ ) Component ID1 Register */
  __IM  uint32_t D_CIDR2;                /*!< Offset: 0x1FF8 (R/ ) Component ID2 Register */
  __IM  uint32_t D_CIDR3;                /*!< Offset: 0x1FFC (R/ ) Component ID3 Register */

  __IOM uint32_t C_CTLR;                 /*!< Offset: 0x2000 (R/W) CPU Interface Control Register */
  __IOM uint32_t C_PMR;                  /*!< Offset: 0x2004 (R/W) Interrupt Priority Mask Register */
  __IOM uint32_t C_BPR;                  /*!< Offset: 0x2008 (R/W) Binary Point Register */
  __IM  uint32_t C_IAR;                  /*!< Offset: 0x200C (R/ ) Interrupt Acknowledge Register */
  __OM  uint32_t C_EOIR;                 /*!< Offset: 0x2010 ( /W) End Of Interrupt Register */
  __IM  uint32_t C_RPR;                  /*!< Offset: 0x2014 (R/ ) Running Priority Register */
  __IM  uint32_t C_HPPIR;                /*!< Offset: 0x2018 (R/ ) Highest Priority Pending Interrupt Register */
  __IOM uint32_t C_ABPR;                 /*!< Offset: 0x201C (R/W) Aliased Binary Point Register */
  __IM  uint32_t C_AIAR;                 /*!< Offset: 0x2020 (R/ ) Aliased Interrupt Acknowledge Register */
  __OM  uint32_t C_AEOIR;                /*!< Offset: 0x2024 ( /W) Aliased End Of Interrupt Register */
  __IM  uint32_t C_AHPPIR;               /*!< Offset: 0x2028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
        uint32_t RESERVED15[41];
  __IOM uint32_t C_APR0;                 /*!< Offset: 0x20D0 (R/W) Active Priority Register */
        uint32_t RESERVED16[3];
  __IOM uint32_t C_NSAPR0;               /*!< Offset: 0x20E0 (R/W) Non-secure Active Priority Register */
        uint32_t RESERVED17[6];
  __IM  uint32_t C_IIDR;                 /*!< Offset: 0x20FC (R/ ) CPU Interface Identification Register */
        uint32_t RESERVED18[960];
  __OM  uint32_t C_DIR;                  /*!< Offset: 0x3000 ( /W) Deactivate Interrupt Register */
} GIC_Type;

C_CTLR

C_IAR：中断通知寄存器；C_EOIR：中断结束寄存器

协处理器

cp0 - cp15 主要使用cp10.11.15 coprocessor

c0 - MIDR

c1 - SCTLR4

汇编代码

复制代码

mrc p15,0,r0,c1,c0,0
bic r0, r0, #(1 << 13)
orr r0, r0, #(1 << 12)
mcr p15,0,r0,c1,c0,0

c12 - VBAR

配置成0后可以修改该寄存器重新映射到其他地址

GPIO1_Combined_16_31_IRQn =99

c15 - CBAR

复制代码

mrc p15, 4, r0, c15, c0, 0

获取GIC基地址

MRC / MCR

MRC：读取cp15寄存器数据

MCR：向cp15寄存器中写入数据

复制代码

MCR<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>}
MRC<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>}
mrc p15, 0, r0, c1, c0, 0 // 读取SCTLR寄存器数据到r0
bic r0, r0, #(1 <<13)
orr r0, r0, #(1 << 12)
mcr p15, 0, r0, c1, c0, 0 // 将r0数据写回到SCTLR寄存器
mcr p15, 0, r0, c12, c0, 0
mrc p15, 4, r1, c15, c0, 0 // 将CBAR寄存器中GIC基地址读取到r1寄存器

异常向量表基地址映射 icache打开

步骤

中断源 -> 中断控制器GIC -> 中断处理器内核kernal

此处示例为按键按下产生一个中断

此处使能IRQ中断后会切换工作模式到IRQ模式（自动）然后执行中断服务函数