已知d为一个8位数,请在每个时钟周期分别输出该数乘1/3/7/8,并输出一个信号通知此时刻输入的d有效(d给出的信号的上升沿表示写入有效)


`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
parameter flag_max = 2'd3;
reg[1:0] flag;
reg[10:0] out_reg;
always@(posedge clk or negedge rst) begin
if(!rst) begin
flag <= 2'b0;
end
else if(flag == flag_max) begin
flag<= 2'b0;
end
else begin
flag <= flag + 1'b1;
end
end
always@(posedge clk or negedge rst)
begin
if(!rst)begin
input_grant <= 0;
out <= 0;
end
else begin
case(flag)
2'b0: begin
input_grant <= 1'b1;
out_reg <= d;
out <= d;
end
2'd1: begin
input_grant <= 1'b0;
out <= out_reg *3;
end
2'd2: begin
input_grant <= 1'b0;
out <= out_reg *7;
end
2'd3: begin
input_grant <= 1'b0;
out <= out_reg *8;
end
default: begin
out <= 10'd0;
input_grant <=1'b0;
end
endcase
end
end
//*************code***********//
endmodule