verilog计数器中增减操作之资源占用

SDAU20052026-09-20 18:34

安路Anlogic TD Release_2026.1_SP2，器件选择：EG4A20BG256

方法1）case语句

复制代码

module test( input clk,input rst_n,input sw,output reg [3:0] led );

always @(posedge clk or negedge rst_n)
   if (!rst_n) 
      led<= 0; 
   else begin   
    case (sw)
      1: led<=led+1;
      default: led<=led-1;
    endcase 
   end
endmodule

方法2）if语句

复制代码

module test( input clk,input rst_n,input sw,output reg [3:0] led  );

always @(posedge clk or negedge rst_n)
   if (!rst_n) 
      led<= 0; 
   else begin   
    if (sw)led<=led+1;
    else led<=led-1;
    end
endmodule

方法3）条件运算符? :

复制代码

module test( input clk,input rst_n,input sw,output reg [3:0] led  );

always @(posedge clk or negedge rst_n)
   if (!rst_n) 
      led<= 0; 
   else begin   
    led<=sw?(led+1):(led-1);
    end
endmodule

方法4）2*sw-1

复制代码

module test( input clk,input rst_n,input sw,output reg [3:0] led  );

always @(posedge clk or negedge rst_n)
   if (!rst_n) 
      led<= 0; 
   else begin   
    led<=led+2*sw-1;
    end
endmodule

资源占用比较：方法4占用资源最少！

|---------|-----|-----|-----------|-----------|------|------|
| 方法 | not | DFF | MACRO_ADD | MACRO_MUX | lut4 | lut5 |
| case | 2 | 4 | 2 | 3 | 3 | 1 |
| if | 2 | 4 | 2 | 3 | 3 | 1 |
| ? : | 2 | 4 | 2 | 3 | 3 | 1 |
| 2*sw-1 | 1 | 4 | 2 | 0 | 3 | 1 |