[HDLBits] Fsm hdlc

Synchronous HDLC framing involves decoding a continuous bit stream of data to look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a "flag" that indicate frame boundaries. To avoid the data stream from accidentally containing "flags", the sender inserts a zero after every 5 consecutive 1s which the receiver must detect and discard. We also need to signal an error if there are 7 or more consecutive 1s.

Create a finite state machine to recognize these three sequences:

• 0111110: Signal a bit needs to be discarded (disc).
• 01111110: Flag the beginning/end of a frame (flag).
• 01111111...: Error (7 or more 1s) (err).

When the FSM is reset, it should be in a state that behaves as though the previous input were 0.

Here are some example sequences that illustrate the desired operation.

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
	//0-5识别为1，5为0跳discard，为1跳6.6为1跳error，为0跳flag
    reg [3:0]state,next;
    parameter discard=7,flagg=8,error=9;
    always@(*)begin
        case(state)
            0:next<=in?1:0;
            1:next<=in?2:0;
            2:next<=in?3:0;
            3:next<=in?4:0;
            4:next<=in?5:0;
            5:next<=in?6:discard;
            6:next<=in?error:flagg;
            discard:next<=in?1:0;
            flagg:next<=in?1:0;
            error:next<=in?error:0;
        endcase
    end
    always@(posedge clk) begin
        if(reset)
            state<=0;
        else
            state<=next;
    end
    assign disc=state==discard;
    assign flag=state==flagg;
    assign err=state==error;
endmodule