Verilog复习（二）| 时延

时延分为惯性延迟 （Inertial Delay (Gates) ）和传输延迟（Transport Delay (Nets) ）

示例：

wire  #5  net_1; // 5 unit transport delay

and #4 (z_out, x_in, y_in);  // 4 unit inertial delay
assign #3 z_out = a & b; // 3 unit inertial delay

wire #2 z_out; // 2 unit transport delay
and #3 (z_out, x_in, y_in); // 3 for gate, 2 for wire

wire #3 c;  // 3 unit transport delay
assign #5 c = a & b; // 5 for assign, 3 for wire

---