本文主要讲解Linux平台(Ubuntu)中Scala的安装,由于sbt资源下载速度较慢,建议使用科学上网方法,如果没有也可以尝试一下方法。
Spinal是一个Scala库(使用Java VM的编程语言),因此需要设置Scala环境;有很多方法可以做到这一点。此外,它还生成 VHDL、Verilog 或 SystemVerilog,可供许多不同的工具使用。本节介绍支持的 SpinalHDL 描述到仿真 流程的安装方法,但可能还有其他方法。
在下载 SpinalHDL 工具之前,需要安装 Scala 环境,包括:
- Java JDK,Java 环境
- Scala 2,编译器和库
- SBT ,Scala 程序构建工具
其中sbt安装容易出现下载失败问题。
1 下载和安装cs
Linux终端输入以下命令:
bash
$ sudo apt-get update
$ sudo apt-get install openjdk-17-jdk-headless curl git
$ curl -fL "https://github.com/coursier/launchers/raw/master/cs-x86_64-pc-linux.gz" | gzip -d > cs
$ chmod +x cs
$ ./cs setup # 弹出PATH选项,需要输入y
由于部分资源处于外网,一般会安装较长时间。尤其是sbt安装容易出问题。
成功后输入:
bash
$ source ~/.profile
输入./cs list
查看安装目录。
bash
$ ./cs list
amm
coursier
cs
sbt
sbtn
scala
scala-cli
scalac
scalafmt
1.1 安装sbt
如果终端输入sbt
弹出没有该命令,则可以使用以下方法安装sbt。如果没报错,就跳过这一步。
bash
$ echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | sudo tee /etc/apt/sources.list.d/sbt.list
$ echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee /etc/apt/sources.list.d/sbt_old.list
$ curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add
$ sudo apt-get update
$ sudo apt-get install sbt
1.2 检验sbt安装
查看sbt版本:sbt sbtVersion
bash
$ sbt sbtVersion
[info] Updated file /home/ren/project/build.properties: set sbt.version to 1.10.1
[info] welcome to sbt 1.10.1 (Ubuntu Java 17.0.11)
[info] loading project definition from /home/ren/project
[info] set current project to ren (in build file:/home/ren/)
[info] 1.10.1
1.3 换源
安装完成后,可以进行换源,加快sbt设置进度。
bash
$ cd
$ mkdir .sbt
$ cd.sbt
$ vim repositories
repositories文件内容如下:
bash
[repositories]
local
huaweicloud-maven: https://repo.huaweicloud.com/repository/maven/
maven-central: https://repo1.maven.org/maven2/
huaweicloud-ivy: https://repo.huaweicloud.com/repository/ivy/, [organization]/[module]/(scala_[scalaVersion]/)(sbt_[sbtVersion]/)[revision]/[type]s/[artifact](-[classifier]).[ext]
2 创建工程
现在开始创建工程,可以先从github上拷贝一个基本模板。
2.1 拷贝工程模板与设置版本控制
工程文件夹设置为MySpinalProject
。
bash
$ git clone --depth 1 https://github.com/SpinalHDL/SpinalTemplateSbt.git MySpinalProject
$ cd MySpinalProject
$ rm -rf .git
$ git init # 版本初始化
$ git add . # 添加文件夹内所有文件到git
$ git commit -m "Initial commit from template" # 提交版本
2.2 打开sbt服务器
进入工程文件夹目录,在终端输入sbt
打开服务器。可能还需要更新,需要较长时间:
bash
$ sbt
[info] Updated file /home/ren/Documents/HDL/cs/project/build.properties: set sbt.version to 1.10.1
[info] welcome to sbt 1.10.1 (Ubuntu Java 17.0.11)
[info] loading project definition from /home/ren/Documents/HDL/cs/project
[info] Updating cs-build
https://repo1.maven.org/maven2/jline/jline/2.14.6/jline-2.14.6.pom
100.0% [##########] 19.4 KiB (8.0 KiB / s)
[info] Resolved cs-build dependencies
[info] Fetching artifacts of cs-build
[info] Fetched artifacts of cs-build
[info] set current project to cs (in build file:/home/ren/Documents/HDL/cs/)
[info] sbt server started at local:///home/ren/.sbt/1.0/server/365572ea2bc7621ad534/sock
[info] started sbt server
sbt:cs>
至此sbt环境搭建完成。
2.3 编译工程
在sbt环境下输入compile
编译工程,一般需要10多秒的时间。
bash
sbt:projectname> compile
[info] Updating
https://repo.huaweicloud.com/repository/maven/org/scala-lang/scala-library/2.12...
100.0% [##########] 1.6 KiB (7.5 KiB / s)
...
https://repo.huaweicloud.com/repository/maven/org/scala-lang/scala-compiler/2.1...
100.0% [##########] 10.5 MiB (4.0 MiB / s)
[info] Fetched artifacts of
[info] compiling 4 Scala sources to /home/ren/Documents/HDL/Spinal/MySpinalProject/target/scala-2.12/classes ...
[info] Non-compiled module 'compiler-bridge_2.12' for Scala 2.12.18. Compiling...
[info] Compilation completed in 14.868s.
[success] Total time: 26 s, completed Jul 15, 2024, 8:38:37 PM
sbt:projectname>
2.4 生成Verilog文件
输入runMain projectname.MyTopLevelVerilog
指令,将在/hw/gen内看到新生成的.v文件。
bash
sbt:projectname> runMain projectname.MyTopLevelVerilog
[info] running (fork) projectname.MyTopLevelVerilog
[info] [Runtime] SpinalHDL v1.10.2a git head : a348a60b7e8b6a455c72e1536ec3d74a2ea16935
[info] [Runtime] JVM max memory : 970.0MiB
[info] [Runtime] Current date : 2024.07.15 21:07:47
[info] [Progress] at 0.000 : Elaborate components
[info] [Progress] at 0.299 : Checks and transforms
[info] [Progress] at 0.423 : Generate Verilog to hw/gen
[info] [Done] at 0.515
[success] Total time: 2 s, completed Jul 15, 2024, 9:07:48 PM
sbt:projectname>
打开工程下/hw/gen/MyTopLevel.v
文件,可以看到以下内容:
java
// Generator : SpinalHDL v1.10.2a git head : a348a60b7e8b6a455c72e1536ec3d74a2ea16935
// Component : MyTopLevel
// Git hash : d5948df07d580910b7c357a961226b6bbb83d1b0
`timescale 1ns/1ps
module MyTopLevel (
input wire io_cond0,
input wire io_cond1,
output wire io_flag,
output wire [7:0] io_state,
input wire clk,
input wire reset
);
reg [7:0] counter;
assign io_state = counter;
assign io_flag = ((counter == 8'h0) || io_cond1);
always @(posedge clk or posedge reset) begin
if(reset) begin
counter <= 8'h0;
end else begin
if(io_cond0) begin
counter <= (counter + 8'h01);
end
end
end
endmodule
打开工程下/hw/spinal/projectname/MyTopLevel.scala
,可以看到以下内容:
java
package projectname
import spinal.core._
// Hardware definition
case class MyTopLevel() extends Component {
val io = new Bundle {
val cond0 = in Bool()
val cond1 = in Bool()
val flag = out Bool()
val state = out UInt(8 bits)
}
val counter = Reg(UInt(8 bits)) init 0
when(io.cond0) {
counter := counter + 1
}
io.state := counter
io.flag := (counter === 0) | io.cond1
}
object MyTopLevelVerilog extends App {
Config.spinal.generateVerilog(MyTopLevel())
}
object MyTopLevelVhdl extends App {
Config.spinal.generateVhdl(MyTopLevel())
}
2.5 自动编译并检查
为了方便使用,需要在每次保存源文件时,自动重新生成MyTopLevel.v
。
sbt环境下输入~ runMain projectname.MyTopLevelVerilog
后,它以后就会自动编译源文件并执行 lint 检查。
这样,当您在之后编辑源文件时,您几乎可以实时在终端上打印错误。
bash
sbt:projectname> ~ runMain projectname.MyTopLevelVerilog
[info] running (fork) projectname.MyTopLevelVerilog
[info] [Runtime] SpinalHDL v1.10.2a git head : a348a60b7e8b6a455c72e1536ec3d74a2ea16935
[info] [Runtime] JVM max memory : 970.0MiB
[info] [Runtime] Current date : 2024.07.15 21:08:47
[info] [Progress] at 0.000 : Elaborate components
[info] [Progress] at 0.291 : Checks and transforms
[info] [Progress] at 0.430 : Generate Verilog to hw/gen
[info] [Done] at 0.507
[success] Total time: 1 s, completed Jul 15, 2024, 9:08:48 PM
[info] 1. Monitoring source files for projectname/runMain projectname.MyTopLevelVerilog...
[info] Press <enter> to interrupt or '?' for more options.
您可以按 Enter 停止自动生成,然后按Ctrl-D
退出 sbt。
也可以直接从终端启动它,而不使用 sbt 的交互式提示:
bash
sbt "~ runMain mylib.MyTopLevelVerilog"
参考链接:
https://spinalhdl.github.io/SpinalDoc-RTD/zh_CN/SpinalHDL/Getting Started/Install and setup.html#
https://www.scala-sbt.org/download/
https://blog.csdn.net/Weary_PJ/article/details/109152272