循环序列生成与并串转换模块设计

爱吃汽的小橘2026-09-22 15:26

编写一个模块，实现循环输出序列001011。

复制代码

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);

reg [5:0] data_gen;

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_gen <= 6'b001011;
	end
	else begin
		data_gen <= {data_gen[4:0],data_gen[5]};
	end
end

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data <= 'd0;
	end
	else begin
		data <= data_gen[5];
	end
end


endmodule

设计一个模块进行并串转换，要求每四位d输为转到一位dout输出，输出valid_in表示此时的输入有效

信号示意图：

clk为时钟

rst为低电平复位

valid_in 表示输入有效

d 信号输入

dout 信号输出

波形示意图：

复制代码

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

//*************code***********//
reg [3:0] d_reg;
reg                 valid;
reg [1:0] cnt;

always@(posedge clk or negedge rst) begin
	if(!rst) begin
		cnt <= 'd0;
	end
	else if(cnt == 'd3) begin
		cnt <= 'd0;
	end
	else cnt <= cnt + 'd1;
end


always@(posedge clk or negedge rst) begin
	if(!rst) begin
		d_reg <= 'd0;
	end
	else if(cnt == 'd3) begin
		d_reg <= d;
	end
	else begin
		d_reg <= d_reg << 1;
	end
end

always@(posedge clk or negedge rst) begin
	if(!rst) begin
		valid <= 'd0;
	end
	else if(cnt == 'd3) begin
		valid <= 'd1;
	end
	else valid <= 'd0;
end

assign   valid_in = valid;
assign   dout     = d_reg[3];
 


//*************code***********//

endmodule