chipcamp@chipcamp:~/src/riscv$ cat /etc/os-release ##ubuntu22系统@十年旧机器。
PRETTY_NAME="Ubuntu 22.04 LTS"
NAME="Ubuntu"
VERSION_ID="22.04"
VERSION="22.04 (Jammy Jellyfish)"
VERSION_CODENAME=jammy
ID=ubuntu
ID_LIKE=debian
HOME_URL="https://www.ubuntu.com/"
SUPPORT_URL="https://help.ubuntu.com/"
BUG_REPORT_URL="https://bugs.launchpad.net/ubuntu/"
PRIVACY_POLICY_URL="https://www.ubuntu.com/legal/terms-and-policies/privacy-policy"
UBUNTU_CODENAME=jammy
chipcamp@chipcamp:~/src/riscv$ which iverilog
/usr/bin/iverilog
chipcamp@chipcamp:~/src/riscv$ which verilator
/usr/bin/verilator
chipcamp@chipcamp:~/src/riscv$ which gtkwave
/usr/bin/gtkwave
chipcamp@chipcamp:~/src/riscv$ which riscv64-unknown-elf-gcc
/usr/bin/riscv64-unknown-elf-gcc
chipcamp@chipcamp:~/src/riscv$
chipcamp@chipcamp:~/src/riscv$ dpkg-query -S /usr/bin/iverilog /usr/bin/verilator /usr/bin/gtkwave /usr/bin/riscv64-unknown-elf-gcc
iverilog: /usr/bin/iverilog
verilator: /usr/bin/verilator
gtkwave: /usr/bin/gtkwave
gcc-riscv64-unknown-elf: /usr/bin/riscv64-unknown-elf-gcc
------以上所有的软件，都是使用apt-get install安装的，这是本文所说的"0依赖"。
chipcamp@chipcamp:~/src/riscv$ git clone https://gitcode.com/chipcamp/picorv32.git
Cloning into 'picorv32'...
remote: Enumerating objects: 2963, done.
remote: Total 2963 (delta 0), reused 0 (delta 0), pack-reused 2963 (from 1)
Receiving objects: 100% (2963/2963), 953.37 KiB | 156.00 KiB/s, done.
Resolving deltas: 100% (1931/1931), done.
chipcamp@chipcamp:~/src/riscv$ cd picorv32/
chipcamp@chipcamp:~/src/riscv/picorv32$ ls -la
total 236
drwxrwxr-x 10 chipcamp chipcamp 4096 Oct 7 09:33 .
drwxrwxr-x 3 chipcamp chipcamp 4096 Oct 7 09:32 ..
drwxrwxr-x 2 chipcamp chipcamp 4096 Oct 7 09:33 comments
-rw-rw-r-- 1 chipcamp chipcamp 777 Oct 7 09:33 COPYING
drwxrwxr-x 2 chipcamp chipcamp 4096 Oct 7 09:33 dhrystone
drwxrwxr-x 2 chipcamp chipcamp 4096 Oct 7 09:33 firmware
drwxrwxr-x 8 chipcamp chipcamp 4096 Oct 7 09:33 .git
drwxrwxr-x 3 chipcamp chipcamp 4096 Oct 7 09:33 .github
-rw-rw-r-- 1 chipcamp chipcamp 734 Oct 7 09:33 .gitignore
-rw-rw-r-- 1 chipcamp chipcamp 8991 Oct 7 09:33 Makefile
-rw-rw-r-- 1 chipcamp chipcamp 1665 Oct 7 09:33 picorv32.core
-rw-rw-r-- 1 chipcamp chipcamp 94657 Oct 7 09:33 picorv32.v
drwxrwxr-x 2 chipcamp chipcamp 4096 Oct 7 09:33 picosoc
-rw-rw-r-- 1 chipcamp chipcamp 30703 Oct 7 09:33 README.md
drwxrwxr-x 14 chipcamp chipcamp 4096 Oct 7 09:33 scripts
-rw-rw-r-- 1 chipcamp chipcamp 5505 Oct 7 09:33 shell.nix
-rw-rw-r-- 1 chipcamp chipcamp 2551 Oct 7 09:33 showtrace.py
-rw-rw-r-- 1 chipcamp chipcamp 1164 Oct 7 09:33 testbench.cc
-rw-rw-r-- 1 chipcamp chipcamp 2318 Oct 7 09:33 testbench_ez.v
-rw-rw-r-- 1 chipcamp chipcamp 12938 Oct 7 09:33 testbench.v
-rw-rw-r-- 1 chipcamp chipcamp 6233 Oct 7 09:33 testbench_wb.v
drwxrwxr-x 2 chipcamp chipcamp 4096 Oct 7 09:33 tests
chipcamp@chipcamp:~/src/riscv/picorv32$
chipcamp@chipcamp:~/src/riscv/picorv32$ more Makefile
RISCV_GNU_TOOLCHAIN_GIT_REVISION = 411d134
#RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX = /opt/riscv32
RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX = /usr
Give the user some easy overrides for local configuration quirks.
If you change one of these and it breaks, then you get to keep both pieces.
SHELL = bash
PYTHON = python3
VERILATOR = verilator
ICARUS_SUFFIX =
IVERILOG = iverilog$(ICARUS_SUFFIX)
VVP = vvp$(ICARUS_SUFFIX)
TEST_OBJS = (addsuffix .o,(basename $(wildcard tests/*.S)))
FIRMWARE_OBJS = firmware/start.o firmware/irq.o firmware/print.o firmware/hello.o firmware/sieve.o firmware/multest.o firmware/stats.o
GCC_WARNS = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings
GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion
#TOOLCHAIN_PREFIX = $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)i/bin/riscv32-unknown-elf-
TOOLCHAIN_PREFIX = $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)/bin/riscv64-unknown-elf-
COMPRESSED_ISA = C
Add things like "export http_proxy=... https_proxy=..." here
GIT_ENV = true
test: testbench.vvp firmware/firmware.hex
(VVP) -N <
test_vcd: testbench.vvp firmware/firmware.hex
(VVP) -N < +vcd +trace +noerror
test_rvf: testbench_rvf.vvp firmware/firmware.hex
(VVP) -N < +vcd +trace +noerror
test_wb: testbench_wb.vvp firmware/firmware.hex
(VVP) -N <
test_wb_vcd: testbench_wb.vvp firmware/firmware.hex
(VVP) -N < +vcd +trace +noerror
test_ez: testbench_ez.vvp
(VVP) -N <
test_ez_vcd: testbench_ez.vvp
(VVP) -N < +vcd
chipcamp@chipcamp:~/src/riscv/picorv32$ make test_ez
iverilog -o testbench_ez.vvp -DCOMPRESSED_ISA testbench_ez.v picorv32.v
chmod -x testbench_ez.vvp
vvp -N testbench_ez.vvp
ifetch 0x00000000: 0x3fc00093
ifetch 0x00000004: 0x0000a023
ifetch 0x00000008: 0x0000a103
write 0x000003fc: 0x00000000 (wstrb=1111)
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000000
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000001 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000001
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000002 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000002
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000003 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000003
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000004 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000004
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000005 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000005
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000006 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000006
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000007 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000007
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000008 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000008
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000009 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000009
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000000a (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000000a
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000000b (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000000b
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000000c (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000000c
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000000d (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000000d
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000000e (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000000e
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000000f (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000000f
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000010 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000010
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000011 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000011
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000012 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000012
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000013 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000013
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000014 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000014
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000015 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000015
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000016 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000016
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000017 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000017
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000018 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000018
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000019 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000019
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000001a (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000001a
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000001b (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000001b
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000001c (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000001c
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000001d (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000001d
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000001e (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000001e
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000001f (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000001f
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000020 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000020
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000021 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000021
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000022 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000022
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000023 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000023
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000024 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000024
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000025 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000025
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000026 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000026
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000027 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000027
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000028 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000028
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000029 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000029
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000002a (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000002a
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000002b (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000002b
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000002c (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000002c
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
chipcamp@chipcamp:~/src/riscv/picorv32$ make
iverilog -o testbench.vvp -DCOMPRESSED_ISA testbench.v picorv32.v
chmod -x testbench.vvp
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imc -o firmware/start.o firmware/start.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32ic -Os --std=c99 -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic -ffreestanding -nostdlib -o firmware/irq.o firmware/irq.c
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32ic -Os --std=c99 -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic -ffreestanding -nostdlib -o firmware/print.o firmware/print.c
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32ic -Os --std=c99 -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic -ffreestanding -nostdlib -o firmware/hello.o firmware/hello.c
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32ic -Os --std=c99 -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic -ffreestanding -nostdlib -o firmware/sieve.o firmware/sieve.c
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32ic -Os --std=c99 -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic -ffreestanding -nostdlib -o firmware/multest.o firmware/multest.c
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32ic -Os --std=c99 -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic -ffreestanding -nostdlib -o firmware/stats.o firmware/stats.c
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/addi.o -DTEST_FUNC_NAME=addi \
-DTEST_FUNC_TXT='"addi"' -DTEST_FUNC_RET=addi_ret tests/addi.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/add.o -DTEST_FUNC_NAME=add \
-DTEST_FUNC_TXT='"add"' -DTEST_FUNC_RET=add_ret tests/add.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/andi.o -DTEST_FUNC_NAME=andi \
-DTEST_FUNC_TXT='"andi"' -DTEST_FUNC_RET=andi_ret tests/andi.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/and.o -DTEST_FUNC_NAME=and \
-DTEST_FUNC_TXT='"and"' -DTEST_FUNC_RET=and_ret tests/and.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/auipc.o -DTEST_FUNC_NAME=auipc \
-DTEST_FUNC_TXT='"auipc"' -DTEST_FUNC_RET=auipc_ret tests/auipc.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/beq.o -DTEST_FUNC_NAME=beq \
-DTEST_FUNC_TXT='"beq"' -DTEST_FUNC_RET=beq_ret tests/beq.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/bge.o -DTEST_FUNC_NAME=bge \
-DTEST_FUNC_TXT='"bge"' -DTEST_FUNC_RET=bge_ret tests/bge.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/bgeu.o -DTEST_FUNC_NAME=bgeu \
-DTEST_FUNC_TXT='"bgeu"' -DTEST_FUNC_RET=bgeu_ret tests/bgeu.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/blt.o -DTEST_FUNC_NAME=blt \
-DTEST_FUNC_TXT='"blt"' -DTEST_FUNC_RET=blt_ret tests/blt.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/bltu.o -DTEST_FUNC_NAME=bltu \
-DTEST_FUNC_TXT='"bltu"' -DTEST_FUNC_RET=bltu_ret tests/bltu.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/bne.o -DTEST_FUNC_NAME=bne \
-DTEST_FUNC_TXT='"bne"' -DTEST_FUNC_RET=bne_ret tests/bne.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/div.o -DTEST_FUNC_NAME=div \
-DTEST_FUNC_TXT='"div"' -DTEST_FUNC_RET=div_ret tests/div.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/divu.o -DTEST_FUNC_NAME=divu \
-DTEST_FUNC_TXT='"divu"' -DTEST_FUNC_RET=divu_ret tests/divu.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/jalr.o -DTEST_FUNC_NAME=jalr \
-DTEST_FUNC_TXT='"jalr"' -DTEST_FUNC_RET=jalr_ret tests/jalr.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/jal.o -DTEST_FUNC_NAME=jal \
-DTEST_FUNC_TXT='"jal"' -DTEST_FUNC_RET=jal_ret tests/jal.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/j.o -DTEST_FUNC_NAME=j \
-DTEST_FUNC_TXT='"j"' -DTEST_FUNC_RET=j_ret tests/j.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/lb.o -DTEST_FUNC_NAME=lb \
-DTEST_FUNC_TXT='"lb"' -DTEST_FUNC_RET=lb_ret tests/lb.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/lbu.o -DTEST_FUNC_NAME=lbu \
-DTEST_FUNC_TXT='"lbu"' -DTEST_FUNC_RET=lbu_ret tests/lbu.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/lh.o -DTEST_FUNC_NAME=lh \
-DTEST_FUNC_TXT='"lh"' -DTEST_FUNC_RET=lh_ret tests/lh.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/lhu.o -DTEST_FUNC_NAME=lhu \
-DTEST_FUNC_TXT='"lhu"' -DTEST_FUNC_RET=lhu_ret tests/lhu.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/lui.o -DTEST_FUNC_NAME=lui \
-DTEST_FUNC_TXT='"lui"' -DTEST_FUNC_RET=lui_ret tests/lui.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/lw.o -DTEST_FUNC_NAME=lw \
-DTEST_FUNC_TXT='"lw"' -DTEST_FUNC_RET=lw_ret tests/lw.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/mulh.o -DTEST_FUNC_NAME=mulh \
-DTEST_FUNC_TXT='"mulh"' -DTEST_FUNC_RET=mulh_ret tests/mulh.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/mulhsu.o -DTEST_FUNC_NAME=mulhsu \
-DTEST_FUNC_TXT='"mulhsu"' -DTEST_FUNC_RET=mulhsu_ret tests/mulhsu.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/mulhu.o -DTEST_FUNC_NAME=mulhu \
-DTEST_FUNC_TXT='"mulhu"' -DTEST_FUNC_RET=mulhu_ret tests/mulhu.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/mul.o -DTEST_FUNC_NAME=mul \
-DTEST_FUNC_TXT='"mul"' -DTEST_FUNC_RET=mul_ret tests/mul.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/ori.o -DTEST_FUNC_NAME=ori \
-DTEST_FUNC_TXT='"ori"' -DTEST_FUNC_RET=ori_ret tests/ori.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/or.o -DTEST_FUNC_NAME=or \
-DTEST_FUNC_TXT='"or"' -DTEST_FUNC_RET=or_ret tests/or.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/rem.o -DTEST_FUNC_NAME=rem \
-DTEST_FUNC_TXT='"rem"' -DTEST_FUNC_RET=rem_ret tests/rem.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/remu.o -DTEST_FUNC_NAME=remu \
-DTEST_FUNC_TXT='"remu"' -DTEST_FUNC_RET=remu_ret tests/remu.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/sb.o -DTEST_FUNC_NAME=sb \
-DTEST_FUNC_TXT='"sb"' -DTEST_FUNC_RET=sb_ret tests/sb.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/sh.o -DTEST_FUNC_NAME=sh \
-DTEST_FUNC_TXT='"sh"' -DTEST_FUNC_RET=sh_ret tests/sh.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/simple.o -DTEST_FUNC_NAME=simple \
-DTEST_FUNC_TXT='"simple"' -DTEST_FUNC_RET=simple_ret tests/simple.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/slli.o -DTEST_FUNC_NAME=slli \
-DTEST_FUNC_TXT='"slli"' -DTEST_FUNC_RET=slli_ret tests/slli.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/sll.o -DTEST_FUNC_NAME=sll \
-DTEST_FUNC_TXT='"sll"' -DTEST_FUNC_RET=sll_ret tests/sll.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/slti.o -DTEST_FUNC_NAME=slti \
-DTEST_FUNC_TXT='"slti"' -DTEST_FUNC_RET=slti_ret tests/slti.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/slt.o -DTEST_FUNC_NAME=slt \
-DTEST_FUNC_TXT='"slt"' -DTEST_FUNC_RET=slt_ret tests/slt.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/srai.o -DTEST_FUNC_NAME=srai \
-DTEST_FUNC_TXT='"srai"' -DTEST_FUNC_RET=srai_ret tests/srai.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/sra.o -DTEST_FUNC_NAME=sra \
-DTEST_FUNC_TXT='"sra"' -DTEST_FUNC_RET=sra_ret tests/sra.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/srli.o -DTEST_FUNC_NAME=srli \
-DTEST_FUNC_TXT='"srli"' -DTEST_FUNC_RET=srli_ret tests/srli.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/srl.o -DTEST_FUNC_NAME=srl \
-DTEST_FUNC_TXT='"srl"' -DTEST_FUNC_RET=srl_ret tests/srl.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/sub.o -DTEST_FUNC_NAME=sub \
-DTEST_FUNC_TXT='"sub"' -DTEST_FUNC_RET=sub_ret tests/sub.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/sw.o -DTEST_FUNC_NAME=sw \
-DTEST_FUNC_TXT='"sw"' -DTEST_FUNC_RET=sw_ret tests/sw.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/xori.o -DTEST_FUNC_NAME=xori \
-DTEST_FUNC_TXT='"xori"' -DTEST_FUNC_RET=xori_ret tests/xori.S
/usr/bin/riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32im -o tests/xor.o -DTEST_FUNC_NAME=xor \
-DTEST_FUNC_TXT='"xor"' -DTEST_FUNC_RET=xor_ret tests/xor.S
/usr/bin/riscv64-unknown-elf-gcc -Os -mabi=ilp32 -march=rv32imc -ffreestanding -nostdlib -o firmware/firmware.elf \
-Wl,--build-id=none,-Bstatic,-T,firmware/sections.lds,-Map,firmware/firmware.map,--strip-debug \
firmware/start.o firmware/irq.o firmware/print.o firmware/hello.o firmware/sieve.o firmware/multest.o firmware/stats.o tests/addi.o tests/add.o tests/andi.o tests/and.o tests/auipc.o tests/beq.o tests/bge.o tests/bgeu.o tests/blt.o tests/bltu.o tests/bne.o tests/div.o tests/divu.o tests/jalr.o tests/jal.o tests/j.o tests/lb.o tests/lbu.o tests/lh.o tests/lhu.o tests/lui.o tests/lw.o tests/mulh.o tests/mulhsu.o tests/mulhu.o tests/mul.o tests/ori.o tests/or.o tests/rem.o tests/remu.o tests/sb.o tests/sh.o tests/simple.o tests/slli.o tests/sll.o tests/slti.o tests/slt.o tests/srai.o tests/sra.o tests/srli.o tests/srl.o tests/sub.o tests/sw.o tests/xori.o tests/xor.o -lgcc
chmod -x firmware/firmware.elf
/usr/bin/riscv64-unknown-elf-objcopy -O binary firmware/firmware.elf firmware/firmware.bin
chmod -x firmware/firmware.bin
python3 firmware/makehex.py firmware/firmware.bin 32768 > firmware/firmware.hex
vvp -N testbench.vvp
hello world
lui..OK
auipc..OK
j..OK
jal..OK
jalr..OK
beq..OK
bne..OK
blt..OK
bge..OK
bltu..OK
bgeu..OK
lb..OK
lh..OK
lw..OK
lbu..OK
lhu..OK
sb..OK
sh..OK
sw..OK
addi..OK
slti..OK
xori..OK
ori..OK
andi..OK
slli..OK
srli..OK
srai..OK
add..OK
sub..OK
sll..OK
slt..OK
xor..OK
srl..OK
sra..OK
or..OK
and..OK
mulh..OK
mulhsu..OK
mulhu..OK
mul..OK
div..OK
divu..OK
rem..OK
remu..OK
simple..OK
1st prime is 2.
2nd prime is 3.
3rd prime is 5.
4th prime is 7.
5th prime is 11.
6th prime is 13.
7th prime is 17.
8th prime is 19.
9th prime is 23.
10th prime is 29.
11th prime is 31.
12th prime is 37.
13th prime is 41.
14th prime is 43.
15th prime is 47.
16th prime is 53.
17th prime is 59.
18th prime is 61.
19th prime is 67.
20th prime is 71.
21st prime is 73.
22nd prime is 79.
23rd prime is 83.
24th prime is 89.
25th prime is 97.
26th prime is 101.
27th prime is 103.
28th prime is 107.
29th prime is 109.
30th prime is 113.
31st prime is 127.
checksum: 1772A48F OK
input FFFFFFFF 80000000 FFFFFFFF FFFFFFFF
hard mul 80000000 00000000 80000000 7FFFFFFF
soft mul 80000000 00000000 80000000 7FFFFFFF OK
hard div 80000000 00000000 00000000 80000000
soft div 80000000 00000000 00000000 80000000 OK
input 00000000 00000000 00000000 00000000
hard mul 00000000 00000000 00000000 00000000
soft mul 00000000 00000000 00000000 00000000 OK
hard div FFFFFFFF FFFFFFFF 00000000 00000000
soft div FFFFFFFF FFFFFFFF 00000000 00000000 OK
input FFFFFFFF 8B578493 00000000 00000000
hard mul 00000000 00000000 00000000 00000000
soft mul 00000000 00000000 00000000 00000000 OK
hard div FFFFFFFF FFFFFFFF 8B578493 8B578493
soft div FFFFFFFF FFFFFFFF 8B578493 8B578493 OK
input 00000000 6F038AFB 00000000 00000000
hard mul 00000000 00000000 00000000 00000000
soft mul 00000000 00000000 00000000 00000000 OK
hard div FFFFFFFF FFFFFFFF 6F038AFB 6F038AFB
soft div FFFFFFFF FFFFFFFF 6F038AFB 6F038AFB OK
input 00000000 1BFC9C22 FFFFFFFF 876B9BDE
hard mul 67CDFB7C F2D15DD3 0ECDF9F5 0ECDF9F5
soft mul 67CDFB7C F2D15DD3 0ECDF9F5 0ECDF9F5 OK
hard div 00000000 00000000 1BFC9C22 1BFC9C22
soft div 00000000 00000000 1BFC9C22 1BFC9C22 OK
input 00000000 76141B16 00000000 5BA2940D
hard mul 949A181E 2A4422A3 2A4422A3 2A4422A3
soft mul 949A181E 2A4422A3 2A4422A3 2A4422A3 OK
hard div 00000001 00000001 1A718709 1A718709
soft div 00000001 00000001 1A718709 1A718709 OK
input 00000000 2D45231C FFFFFFFF ADFA166F
hard mul C756A124 F17ECF19 1EC3F235 1EC3F235
soft mul C756A124 F17ECF19 1EC3F235 1EC3F235 OK
hard div 00000000 00000000 2D45231C 2D45231C
soft div 00000000 00000000 2D45231C 2D45231C OK
input 00000000 09C7BF74 00000000 3B014C60
hard mul 73323B80 024115D2 024115D2 024115D2
soft mul 73323B80 024115D2 024115D2 024115D2 OK
hard div 00000000 00000000 09C7BF74 09C7BF74
soft div 00000000 00000000 09C7BF74 09C7BF74 OK
input 00000000 4325E1E6 00000000 1C32932A
hard mul 0BDA21BC 076568B5 076568B5 076568B5
soft mul 0BDA21BC 076568B5 076568B5 076568B5 OK
hard div 00000002 00000002 0AC0BB92 0AC0BB92
soft div 00000002 00000002 0AC0BB92 0AC0BB92 OK
input FFFFFFFF 84A97421 FFFFFFFF EF8D27D7
hard mul 002E8EB7 07ECBD6D 8C96318E 7C235965
soft mul 002E8EB7 07ECBD6D 8C96318E 7C235965 OK
hard div 00000007 00000000 F7CD5D40 84A97421
soft div 00000007 00000000 F7CD5D40 84A97421 OK
input 00000000 258BAFEC 00000000 5EB6FD37
hard mul D7A707B4 0DE4210A 0DE4210A 0DE4210A
soft mul D7A707B4 0DE4210A 0DE4210A 0DE4210A OK
hard div 00000000 00000000 258BAFEC 258BAFEC
soft div 00000000 00000000 258BAFEC 258BAFEC OK
input FFFFFFFF A31BEA5F 00000000 145CCB97
hard mul FE749309 F89C8277 F89C8277 0CF94E0E
soft mul FE749309 F89C8277 F89C8277 0CF94E0E OK
hard div FFFFFFFC 00000008 F48F18BB 00358DA7
soft div FFFFFFFC 00000008 F48F18BB 00358DA7 OK
input 00000000 28E3CD00 00000000 793F5181
hard mul 21A74D00 135DC8F9 135DC8F9 135DC8F9
soft mul 21A74D00 135DC8F9 135DC8F9 135DC8F9 OK
hard div 00000000 00000000 28E3CD00 28E3CD00
soft div 00000000 00000000 28E3CD00 28E3CD00 OK
input FFFFFFFF F2E838C6 00000000 4BE0C5FE
hard mul 6558B274 FC1E89B3 FC1E89B3 47FF4FB1
soft mul 6558B274 FC1E89B3 FC1E89B3 47FF4FB1 OK
hard div 00000000 00000003 F2E838C6 0F45E6CC
soft div 00000000 00000003 F2E838C6 0F45E6CC OK
input 00000000 38BAA671 FFFFFFFF E2E2B92B
hard mul 1B639DFB F98C5E4E 324704BF 324704BF
soft mul 1B639DFB F98C5E4E 324704BF 324704BF OK
hard div FFFFFFFF 00000000 1B9D5F9C 38BAA671
soft div FFFFFFFF 00000000 1B9D5F9C 38BAA671 OK
Cycle counter ......... 420423
Instruction counter .... 89410
CPI: 4.70
DONE
EBREAK instruction at 0x0000072C
pc 0000072F x8 00000000 x16 E2E2B92B x24 00000000
x1 000006FE x9 00000000 x17 00000000 x25 00000000
x2 00020000 x10 20000000 x18 00000000 x26 00000000
x3 DEADBEEF x11 075BCD15 x19 00003A74 x27 00000000
x4 DEADBEEF x12 0000004F x20 00000000 x28 0000E8EA
x5 0000107A x13 0000004E x21 00000000 x29 38BAA671
x6 38BAA671 x14 00000045 x22 00000000 x30 38BAA671
x7 00000000 x15 0000000A x23 00000000 x31 00000000
Number of fast external IRQs counted: 52
Number of slow external IRQs counted: 6
Number of timer IRQs counted: 22
TRAP after 460537 clock cycles
ALL TESTS PASSED.
chipcamp@chipcamp:~/src/riscv/picorv32$ date
Wed Oct 7 09:38:24 AM CST 2026
chipcamp@chipcamp:~/src/riscv/picorv32$ make test_ez_vcd
vvp -N testbench_ez.vvp +vcd
VCD info: dumpfile testbench.vcd opened for output.
ifetch 0x00000000: 0x3fc00093
ifetch 0x00000004: 0x0000a023
ifetch 0x00000008: 0x0000a103
write 0x000003fc: 0x00000000 (wstrb=1111)
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000000
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000001 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000001
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000002 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000002
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000003 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000003
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000004 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000004
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000005 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000005
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000006 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000006
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000007 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000007
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000008 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000008
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000009 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000009
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000000a (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000000a
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000000b (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000000b
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000000c (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000000c
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000000d (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000000d
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000000e (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000000e
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000000f (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000000f
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000010 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000010
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000011 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000011
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000012 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000012
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000013 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000013
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000014 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000014
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000015 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000015
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000016 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000016
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000017 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000017
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000018 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000018
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000019 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000019
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000001a (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000001a
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000001b (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000001b
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000001c (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000001c
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000001d (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000001d
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000001e (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000001e
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000001f (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000001f
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000020 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000020
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000021 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000021
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000022 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000022
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000023 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000023
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000024 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000024
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000025 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000025
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000026 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000026
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000027 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000027
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000028 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000028
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x00000029 (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x00000029
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000002a (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000002a
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000002b (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000002b
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
write 0x000003fc: 0x0000002c (wstrb=1111)
ifetch 0x00000008: 0x0000a103
ifetch 0x0000000c: 0x00110113
read 0x000003fc: 0x0000002c
ifetch 0x00000010: 0x0020a023
ifetch 0x00000014: 0xff5ff06f
chipcamp@chipcamp:~/src/riscv/picorv32$ ls -la *.vcd
-rw-rw-r-- 1 chipcamp chipcamp 269234 Oct 7 09:47 testbench.vcd
chipcamp@chipcamp:~/src/riscv/picorv32$ gtkwave testbench.vcd &
1 9145
chipcamp@chipcamp:~/src/riscv/picorv32$
GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
0 start time.
11000000 end time.
chipcamp@chipcamp:~/src/riscv/picorv32$
----这个图里的From 0 sec to 11 us，和上面的11000000 end time是完全对应的，11us等于11000000ps。
----为什么是ps，因为在testbench_ez.v里面timescale 1 ns / 1 ps，定义的最小"分辨率"是1ps，但是clk的反转则是用1 ns为单位的！这个timescale 1 ns / 1 ps，定义了两个时间量纲分别是这个意思！一个是最小分辨率，一个是clk的最小分辨率。
----图中，clk信号翻转是每5ns一次，clk周期则是10ns。100个时钟周期则是1个us，正是图中resetn信号翻转的时刻。
----这个1ps和1ns的时间刻度，以及5ns的clk翻转(10ns的clk周期)，1us时刻的resetn信号翻转，11us的测试结束时间，都都都是在testbench_ez.v里定义的。如下所示。
chipcamp@chipcamp:~/src/riscv/picorv32$ cat testbench_ez.v
// This is free and unencumbered software released into the public domain.
//
// Anyone is free to copy, modify, publish, use, compile, sell, or
// distribute this software, either in source code form or as a compiled
// binary, for any purpose, commercial or non-commercial, and by any
// means.
`timescale 1 ns / 1 ps
module testbench;
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
if (testplusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (100) @(posedge clk);
resetn <= 1;
repeat (1000) @(posedge clk);
$finish;
end
wire mem_valid;
wire mem_instr;
reg mem_ready;
wire 31:0 mem_addr;
wire 31:0 mem_wdata;
wire 3:0 mem_wstrb;
reg 31:0 mem_rdata;
always @(posedge clk) begin
if (mem_valid && mem_ready) begin
if (mem_instr)
$display("ifetch 0x%08x: 0x%08x", mem_addr, mem_rdata);
else if (mem_wstrb)
$display("write 0x%08x: 0x%08x (wstrb=%b)", mem_addr, mem_wdata, mem_wstrb);
else
$display("read 0x%08x: 0x%08x", mem_addr, mem_rdata);
end
end
picorv32 #(
) uut (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
reg 31:0 memory 0:255;
initial begin
memory0 = 32'h 3fc00093; // li x1,1020
memory1 = 32'h 0000a023; // sw x0,0(x1)
memory2 = 32'h 0000a103; // loop: lw x2,0(x1)
memory3 = 32'h 00110113; // addi x2,x2,1
memory4 = 32'h 0020a023; // sw x2,0(x1)
memory5 = 32'h ff5ff06f; // j <loop>
end
chipcamp@chipcamp:~/src/riscv/picorv32$ make test_verilator
verilator --cc --exe -Wno-lint -trace --top-module picorv32_wrapper testbench.v picorv32.v testbench.cc \
-DCOMPRESSED_ISA --Mdir testbench_verilator_dir
make -C testbench_verilator_dir -f Vpicorv32_wrapper.mk
make1: Entering directory '/home/chipcamp/src/riscv/picorv32/testbench_verilator_dir'
g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Os -c -o testbench.o ../testbench.cc
g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Os -c -o verilated.o /usr/share/verilator/include/verilated.cpp
g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Os -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp
g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Os -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp
/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vpicorv32_wrapper.cpp Vpicorv32_wrapper_picorv32_wrapper.cpp Vpicorv32_wrapper_axi4_memory.cpp Vpicorv32_wrapper__Dpi.cpp Vpicorv32_wrapper__Trace.cpp Vpicorv32_wrapper__Slow.cpp Vpicorv32_wrapper_picorv32_wrapper__Slow.cpp Vpicorv32_wrapper_axi4_memory__Slow.cpp Vpicorv32_wrapper__Syms.cpp Vpicorv32_wrapper__Trace__Slow.cpp > Vpicorv32_wrapper__ALL.cpp
g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Os -c -o Vpicorv32_wrapper__ALL.o Vpicorv32_wrapper__ALL.cpp
ar -cr Vpicorv32_wrapper__ALL.a Vpicorv32_wrapper__ALL.o
ranlib Vpicorv32_wrapper__ALL.a
g++ testbench.o verilated.o verilated_dpi.o verilated_vcd_c.o Vpicorv32_wrapper__ALL.a -o Vpicorv32_wrapper
make1: Leaving directory '/home/chipcamp/src/riscv/picorv32/testbench_verilator_dir'
cp testbench_verilator_dir/Vpicorv32_wrapper testbench_verilator
./testbench_verilator
Built with Verilator 4.038 2020-07-11.
Recommended: Verilator 4.0 or later.
hello world
lui..OK
auipc..OK
j..OK
jal..OK
jalr..OK
beq..OK
bne..OK
blt..OK
bge..OK
bltu..OK
bgeu..OK
lb..OK
lh..OK
lw..OK
lbu..OK
lhu..OK
sb..OK
sh..OK
sw..OK
addi..OK
slti..OK
xori..OK
ori..OK
andi..OK
slli..OK
srli..OK
srai..OK
add..OK
sub..OK
sll..OK
slt..OK
xor..OK
srl..OK
sra..OK
or..OK
and..OK
mulh..OK
mulhsu..OK
mulhu..OK
mul..OK
div..OK
divu..OK
rem..OK
remu..OK
simple..OK
1st prime is 2.
2nd prime is 3.
3rd prime is 5.
4th prime is 7.
5th prime is 11.
6th prime is 13.
7th prime is 17.
8th prime is 19.
9th prime is 23.
10th prime is 29.
11th prime is 31.
12th prime is 37.
13th prime is 41.
14th prime is 43.
15th prime is 47.
16th prime is 53.
17th prime is 59.
18th prime is 61.
19th prime is 67.
20th prime is 71.
21st prime is 73.
22nd prime is 79.
23rd prime is 83.
24th prime is 89.
25th prime is 97.
26th prime is 101.
27th prime is 103.
28th prime is 107.
29th prime is 109.
30th prime is 113.
31st prime is 127.
checksum: 1772A48F OK
input FFFFFFFF 80000000 FFFFFFFF FFFFFFFF
hard mul 80000000 00000000 80000000 7FFFFFFF
soft mul 80000000 00000000 80000000 7FFFFFFF OK
hard div 80000000 00000000 00000000 80000000
soft div 80000000 00000000 00000000 80000000 OK
input 00000000 00000000 00000000 00000000
hard mul 00000000 00000000 00000000 00000000
soft mul 00000000 00000000 00000000 00000000 OK
hard div FFFFFFFF FFFFFFFF 00000000 00000000
soft div FFFFFFFF FFFFFFFF 00000000 00000000 OK
input FFFFFFFF 8B578493 00000000 00000000
hard mul 00000000 00000000 00000000 00000000
soft mul 00000000 00000000 00000000 00000000 OK
hard div FFFFFFFF FFFFFFFF 8B578493 8B578493
soft div FFFFFFFF FFFFFFFF 8B578493 8B578493 OK
input 00000000 6F038AFB 00000000 00000000
hard mul 00000000 00000000 00000000 00000000
soft mul 00000000 00000000 00000000 00000000 OK
hard div FFFFFFFF FFFFFFFF 6F038AFB 6F038AFB
soft div FFFFFFFF FFFFFFFF 6F038AFB 6F038AFB OK
input 00000000 1BFC9C22 FFFFFFFF 876B9BDE
hard mul 67CDFB7C F2D15DD3 0ECDF9F5 0ECDF9F5
soft mul 67CDFB7C F2D15DD3 0ECDF9F5 0ECDF9F5 OK
hard div 00000000 00000000 1BFC9C22 1BFC9C22
soft div 00000000 00000000 1BFC9C22 1BFC9C22 OK
input 00000000 76141B16 00000000 5BA2940D
hard mul 949A181E 2A4422A3 2A4422A3 2A4422A3
soft mul 949A181E 2A4422A3 2A4422A3 2A4422A3 OK
hard div 00000001 00000001 1A718709 1A718709
soft div 00000001 00000001 1A718709 1A718709 OK
input 00000000 2D45231C FFFFFFFF ADFA166F
hard mul C756A124 F17ECF19 1EC3F235 1EC3F235
soft mul C756A124 F17ECF19 1EC3F235 1EC3F235 OK
hard div 00000000 00000000 2D45231C 2D45231C
soft div 00000000 00000000 2D45231C 2D45231C OK
input 00000000 09C7BF74 00000000 3B014C60
hard mul 73323B80 024115D2 024115D2 024115D2
soft mul 73323B80 024115D2 024115D2 024115D2 OK
hard div 00000000 00000000 09C7BF74 09C7BF74
soft div 00000000 00000000 09C7BF74 09C7BF74 OK
input 00000000 4325E1E6 00000000 1C32932A
hard mul 0BDA21BC 076568B5 076568B5 076568B5
soft mul 0BDA21BC 076568B5 076568B5 076568B5 OK
hard div 00000002 00000002 0AC0BB92 0AC0BB92
soft div 00000002 00000002 0AC0BB92 0AC0BB92 OK
input FFFFFFFF 84A97421 FFFFFFFF EF8D27D7
hard mul 002E8EB7 07ECBD6D 8C96318E 7C235965
soft mul 002E8EB7 07ECBD6D 8C96318E 7C235965 OK
hard div 00000007 00000000 F7CD5D40 84A97421
soft div 00000007 00000000 F7CD5D40 84A97421 OK
input 00000000 258BAFEC 00000000 5EB6FD37
hard mul D7A707B4 0DE4210A 0DE4210A 0DE4210A
soft mul D7A707B4 0DE4210A 0DE4210A 0DE4210A OK
hard div 00000000 00000000 258BAFEC 258BAFEC
soft div 00000000 00000000 258BAFEC 258BAFEC OK
input FFFFFFFF A31BEA5F 00000000 145CCB97
hard mul FE749309 F89C8277 F89C8277 0CF94E0E
soft mul FE749309 F89C8277 F89C8277 0CF94E0E OK
hard div FFFFFFFC 00000008 F48F18BB 00358DA7
soft div FFFFFFFC 00000008 F48F18BB 00358DA7 OK
input 00000000 28E3CD00 00000000 793F5181
hard mul 21A74D00 135DC8F9 135DC8F9 135DC8F9
soft mul 21A74D00 135DC8F9 135DC8F9 135DC8F9 OK
hard div 00000000 00000000 28E3CD00 28E3CD00
soft div 00000000 00000000 28E3CD00 28E3CD00 OK
input FFFFFFFF F2E838C6 00000000 4BE0C5FE
hard mul 6558B274 FC1E89B3 FC1E89B3 47FF4FB1
soft mul 6558B274 FC1E89B3 FC1E89B3 47FF4FB1 OK
hard div 00000000 00000003 F2E838C6 0F45E6CC
soft div 00000000 00000003 F2E838C6 0F45E6CC OK
input 00000000 38BAA671 FFFFFFFF E2E2B92B
hard mul 1B639DFB F98C5E4E 324704BF 324704BF
soft mul 1B639DFB F98C5E4E 324704BF 324704BF OK
hard div FFFFFFFF 00000000 1B9D5F9C 38BAA671
soft div FFFFFFFF 00000000 1B9D5F9C 38BAA671 OK
Cycle counter ......... 420423
Instruction counter .... 89410
CPI: 4.70
DONE
EBREAK instruction at 0x0000072C
pc 0000072F x8 00000000 x16 E2E2B92B x24 00000000
x1 000006FE x9 00000000 x17 00000000 x25 00000000
x2 00020000 x10 20000000 x18 00000000 x26 00000000
x3 DEADBEEF x11 075BCD15 x19 00003A74 x27 00000000
x4 DEADBEEF x12 0000004F x20 00000000 x28 0000E8EA
x5 0000107A x13 0000004E x21 00000000 x29 38BAA671
x6 38BAA671 x14 00000045 x22 00000000 x30 38BAA671
x7 00000000 x15 0000000A x23 00000000 x31 00000000
Number of fast external IRQs counted: 52
Number of slow external IRQs counted: 6
Number of timer IRQs counted: 22
TRAP after 460536 clock cycles
ALL TESTS PASSED.
- testbench.v:266: Verilog $finish
chipcamp@chipcamp:~/src/riscv/picorv32$ date
Wed Oct 7 10:16:22 AM CST 2026
chipcamp@chipcamp:~/src/riscv/picorv32$
<<<<<<<<<<END完>>>>>>>>>>
关键字：iverilog, verilator, gtkwave, riscv64-unknown-elf-gcc, picorv32, ubuntu, dpkg-query.
摘要：本文记录了Picorv32项目的make过程。第一个是make test_ez，只依赖于iverilog仿真器，CPU RTL上所运行的指令就在tb.v中。第二个是make test，依赖riscv64-unknown-elf-工具套生成firmware.hex。第三个是make test_verilator使用verilator进行仿真。第四个是make test_ez_vcd展示了vcd的生成及gtkwave查看。这些软件在ubuntu下apt直接安装即可，展示了picorv32项目零门槛上手的特点。