Circuits--Sequential--FSM--q5b~q3a

  1. q5b

    module top_module (
    input clk,
    input areset,
    input x,
    output z
    );

    复制代码
     parameter A = 1'b0;
     parameter B = 1'b1;
     
     reg[1:0] state;
     reg[1:0] next_state;
    
     
     always@(*)
         begin
             case(state)
                 A:
                     if(x) next_state = B;
                 	else  next_state = A;
                 B:
                     next_state = B;
             endcase
         end
     
     always@(posedge clk or posedge areset)
         begin
             if(areset)
                 state = A;
             else
                 state = next_state;
         end
     
     always@(*)
         begin
             if(state == A)
                 begin
                     if(x)  z = 1'b1;
                     else   z = 1'b0;
                 end
                 
             else
                 begin
                   	if(x) z = 1'b0;
                   	else z = 1'b1;
               	end
         end

    endmodule

  2. q3a

    module top_module(
    input clk,
    input reset,
    input s,
    input w,
    output z
    );

    复制代码
     parameter A = 1'd0;
     parameter B = 1'd1;
     reg[1:0] state;
     reg[1:0] next_state;
     reg[1:0] count;
     reg[1:0] num;
    
     always @(*) begin
         case(state)
             A:
                 begin
                     if(s) next_state = B;
                     else  next_state = A;
                 end
             B:
                 begin
                     next_state = B;
                 end
            
         endcase
     end
    
     always @(posedge clk) begin
         if(reset)
             state <= A;
         else
             state <= next_state;
     end
    
     always @(posedge clk) begin
         if(reset)
             count <= 2'd0;
         else if(count == 2'd2)
             count <= 2'd0;
         else if(state == B)
             count <= count + 1'b1;
     end
    
     always @(posedge clk) begin
         if(reset)
             num <= 1'b0;
         else
             begin
                 if(count == 2'd0)
                     begin
                         if(w) num <= 1'b1;
                         else num <= 1'b0;
                     end 
                 else if(state == B)
                     begin 
                         if(w) num <= num + 1'b1;
                         else  num <= num;
                     end
    
             end
     end
     assign z = (state == B && num == 2'd2 && count == 2'd0);

    endmodule

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