-
q5b
module top_module (
input clk,
input areset,
input x,
output z
);parameter A = 1'b0; parameter B = 1'b1; reg[1:0] state; reg[1:0] next_state; always@(*) begin case(state) A: if(x) next_state = B; else next_state = A; B: next_state = B; endcase end always@(posedge clk or posedge areset) begin if(areset) state = A; else state = next_state; end always@(*) begin if(state == A) begin if(x) z = 1'b1; else z = 1'b0; end else begin if(x) z = 1'b0; else z = 1'b1; end end
endmodule
-
q3a
module top_module(
input clk,
input reset,
input s,
input w,
output z
);parameter A = 1'd0; parameter B = 1'd1; reg[1:0] state; reg[1:0] next_state; reg[1:0] count; reg[1:0] num; always @(*) begin case(state) A: begin if(s) next_state = B; else next_state = A; end B: begin next_state = B; end endcase end always @(posedge clk) begin if(reset) state <= A; else state <= next_state; end always @(posedge clk) begin if(reset) count <= 2'd0; else if(count == 2'd2) count <= 2'd0; else if(state == B) count <= count + 1'b1; end always @(posedge clk) begin if(reset) num <= 1'b0; else begin if(count == 2'd0) begin if(w) num <= 1'b1; else num <= 1'b0; end else if(state == B) begin if(w) num <= num + 1'b1; else num <= num; end end end assign z = (state == B && num == 2'd2 && count == 2'd0);
endmodule
Circuits--Sequential--FSM--q5b~q3a
且听风吟5672024-05-27 9:52
相关推荐
亦枫Leonlew8 分钟前
微积分复习笔记 Calculus Volume 1 - 6.5 Physical Applications冰帝海岸5 小时前
01-spring security认证笔记小二·6 小时前
java基础面试题笔记(基础篇)wusong9999 小时前
mongoDB回顾笔记(一)猫爪笔记9 小时前
前端:HTML (学习笔记)【1】Resurgence039 小时前
【计组笔记】习题pq113_610 小时前
ftdi_sio应用学习笔记 3 - GPIO爱米的前端小笔记10 小时前
前端八股自学笔记分享—页面布局(二)fei_sun12 小时前
【Verilog】第一章作业寒笙LED13 小时前
C++详细笔记(六)string库