Verilog刷题笔记49——Fsm1同步复位

题目：

解题：

module top_module(clk,reset,in,out);
    input clk;
    input reset;
    input in;
    output out;
    
    parameter A=0,B=1;
    reg [1:0]current_state,next_state;
    
    always@(posedge clk)begin
        if(reset)
            current_state=B;
        else
            current_state=next_state;
    end
    
    always@(*)begin
        case(current_state)
            A:next_state=(in==0)?B:A;
            B:next_state=(in==0)?A:B;
        endcase
    end
    
    assign out=(current_state==A)?0:1;
endmodule

结果正确: