2024-7-20
数字软件安装,仿真环境测试
dut重新修改
makefile重新修改
verdi整合完成
dut.v
module dut ( );
reg clk;
initial begin
clk =0;
forever begin
#10 clk = ~clk;
end
end
initial begin
$fsdbDumpfile("verilog.fsdb");
$fsdbDumpvars();
$vcdpluson;
$display("fsdbDumpfilrs is start at %d",$time);
#1e9;
$finish;
end
endmodule
makefile
all:comp run
comp:
vcs -full64 +v2k -sverilog dut.v \
-timescale=1ns/1ps \
-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab \
-debug_acc+all
run:
./simv
verdi:
verdi -full64 -sv dut.v -ssf verilog.fsdb -nologo&
clean:
rm -rf simv*
rm -rf *.vpd
rm -rf *.key
rm -rf csrc