Verilog刷题笔记56

题目:

Exams/2014 q3fsm

Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM examines the value of the input w in the next three clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next three clock cycles, and so on. The timing diagram below illustrates the required values of z for different values of w.

Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input.

解题:

cpp 复制代码
module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);

    parameter A=0,B=1,B1=2,B2=3;
    reg [2:0]state,next_state;
    reg [2:0]cnt;
    always@(posedge clk)begin
        if(reset)
            state=A;
        else
            state=next_state;
    end
    always@(*)begin
        case(state)
            A:next_state=s?B:A;
            B:next_state=B1;
            B1:next_state=B2;
            B2:next_state=B;
            default:next_state=A;
        endcase
    end
    always@(posedge clk)begin
        if(reset)begin
            cnt=0;
        end
        else begin
            case(state)
                A:cnt=0;
                B: cnt=w;
                B1:cnt=w?cnt+1:cnt;
                B2:cnt=w?cnt+1:cnt;
                default:cnt=0;
            endcase
        end
    end
    assign z=((state==B)&(cnt==2))?1:0;

                
endmodule

结果正确:

网上看到另一种解法,记录一下,类似FIFO思想,先进先出。

cpp 复制代码
module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);

	localparam  A  = 1'b0,
			    B  = 1'b1;	
	reg [1:0] state,next_state;
	reg [2:0] data;
	reg [1:0] cnt;
	
	always@(posedge clk)begin
		if(reset)
			state <= A;
		else 
			state <= next_state; 
	end
	
	always@(*)begin
		case (state)
			A: next_state = s?B:A;
			B: next_state = B;
        endcase
	end
	
	always@(posedge clk)begin
		if(reset)
		data <= 3'b0;
		else case (next_state)		
		A: data <= 3'b0;
		B: begin
				data[0] <= w;
				data[1] <= data[0];
				data[2] <= data[1];	
		   end	
        endcase
	end
	
	always@(posedge clk)begin
		if(reset)
			cnt <= 2'h0;
		else if(state == A)
			cnt <= 2'h0;
		else if(cnt==2'h3&&(state == B))
			cnt <= 2'h1;
		else 
			cnt <= cnt+2'h1;
	end
	
	assign z = ((data==3'b011)|(data==3'b101)|(data==3'b110))&&(cnt==2'h3);  
	
endmodule
相关推荐
隐匿7812 小时前
nacos网站
笔记
nnerddboy2 小时前
QT(c++)开发自学笔记:2.TCP/IP
c++·笔记·qt
程序员东岸2 小时前
避坑修链表:从顺序表到单链表的那点事儿(含可跑示例与小项目串联)
数据结构·笔记·学习·程序人生·链表
cycf3 小时前
源同步接口(六)
fpga开发
电子凉冰3 小时前
FPGA强化-简易电压表的设计与验证
fpga开发
赶飞机偏偏下雨3 小时前
【Java笔记】消息队列
java·开发语言·笔记
国科安芯8 小时前
抗辐照MCU芯片在低轨商业卫星原子钟中的适配与优化
单片机·嵌入式硬件·fpga开发·架构·risc-v
黎宇幻生11 小时前
Java全栈学习笔记39
java·笔记·学习
遇印记14 小时前
大二java学习笔记:二维数组
java·笔记·学习
bnsarocket16 小时前
Verilog和FPGA的自学笔记6——计数器(D触发器同步+异步方案)
笔记·fpga开发·verilog·自学·硬件编程