Verilog刷题笔记56

题目:

Exams/2014 q3fsm

Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM examines the value of the input w in the next three clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next three clock cycles, and so on. The timing diagram below illustrates the required values of z for different values of w.

Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input.

解题:

cpp 复制代码
module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);

    parameter A=0,B=1,B1=2,B2=3;
    reg [2:0]state,next_state;
    reg [2:0]cnt;
    always@(posedge clk)begin
        if(reset)
            state=A;
        else
            state=next_state;
    end
    always@(*)begin
        case(state)
            A:next_state=s?B:A;
            B:next_state=B1;
            B1:next_state=B2;
            B2:next_state=B;
            default:next_state=A;
        endcase
    end
    always@(posedge clk)begin
        if(reset)begin
            cnt=0;
        end
        else begin
            case(state)
                A:cnt=0;
                B: cnt=w;
                B1:cnt=w?cnt+1:cnt;
                B2:cnt=w?cnt+1:cnt;
                default:cnt=0;
            endcase
        end
    end
    assign z=((state==B)&(cnt==2))?1:0;

                
endmodule

结果正确:

网上看到另一种解法,记录一下,类似FIFO思想,先进先出。

cpp 复制代码
module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);

	localparam  A  = 1'b0,
			    B  = 1'b1;	
	reg [1:0] state,next_state;
	reg [2:0] data;
	reg [1:0] cnt;
	
	always@(posedge clk)begin
		if(reset)
			state <= A;
		else 
			state <= next_state; 
	end
	
	always@(*)begin
		case (state)
			A: next_state = s?B:A;
			B: next_state = B;
        endcase
	end
	
	always@(posedge clk)begin
		if(reset)
		data <= 3'b0;
		else case (next_state)		
		A: data <= 3'b0;
		B: begin
				data[0] <= w;
				data[1] <= data[0];
				data[2] <= data[1];	
		   end	
        endcase
	end
	
	always@(posedge clk)begin
		if(reset)
			cnt <= 2'h0;
		else if(state == A)
			cnt <= 2'h0;
		else if(cnt==2'h3&&(state == B))
			cnt <= 2'h1;
		else 
			cnt <= cnt+2'h1;
	end
	
	assign z = ((data==3'b011)|(data==3'b101)|(data==3'b110))&&(cnt==2'h3);  
	
endmodule
相关推荐
m0_6786933312 分钟前
深度学习笔记29-RNN实现阿尔茨海默病诊断(Pytorch)
笔记·rnn·深度学习
sigmoidAndRELU1 小时前
读Vista
笔记·stable diffusion·世界模型
Sincerelyplz2 小时前
【Temproal】快速了解Temproal的核心概念以及使用
笔记·后端·开源
Yo_Becky3 小时前
【PyTorch】PyTorch预训练模型缓存位置迁移,也可拓展应用于其他文件的迁移
人工智能·pytorch·经验分享·笔记·python·程序人生·其他
DIY机器人工房3 小时前
0.96寸OLED显示屏 江协科技学习笔记(36个知识点)
笔记·科技·stm32·单片机·嵌入式硬件·学习·江协科技
future14125 小时前
每日问题总结
经验分享·笔记
search75 小时前
Verilog 语法介绍 1-1结构
fpga开发
循环过三天7 小时前
3-1 PID算法改进(积分部分)
笔记·stm32·单片机·学习·算法·pid
之歆7 小时前
Python-封装和解构-set及操作-字典及操作-解析式生成器-内建函数迭代器-学习笔记
笔记·python·学习
DKPT9 小时前
Java组合模式实现方式与测试方法
java·笔记·学习·设计模式·组合模式