fpga异步fifo - 技术栈

复制代码
module top(
    input      wire       clk  ,
    input      wire       rst_n,
    output     wire       tx   
);
//reg
reg  [7:0]cunt  ;//din
reg  [25:0]cunt_num; 
reg  [25:0]cunt1   ;
//wire 
wire      wr_clk;
wire      rd_clk;
wire      locked;
wire      rst   ;
wire      wr_en ;
wire      rd_en ;
wire [7:0]dout  ;
wire      full  ;
wire      empty ;
wire      wr_rst_busy;
wire      rd_rst_busy;
wire      vled   ;
wire      busy   ;

assign rst=(locked==1&&rst_n==1&&wr_rst_busy==0)?1'b0:1'b1;  //高电平复位开始 低电平复位不使能 系统正常运行
//产生一个计数器计数 0~9只产生一次
always @(posedge wr_clk or posedge rst) begin
    if(rst)
        cunt<=0;
    else if(cunt==11)
        cunt<=cunt;
    else
        cunt<=cunt+1;
end

assign wr_en=(cunt>1&&cunt<10&&cunt>0)?1'b1:1'b0;
always @(posedge rd_clk) begin
    if(rst)
        cunt_num<=0;
    else if(busy==0)begin
        if(cunt_num==20)
        cunt_num<=cunt_num;
        else
        cunt_num<=cunt_num+1;
        end
    else
    cunt_num<=0;
end
always @(posedge rd_clk) begin
    if(rst)
        cunt1<=0;
    else if(vled==1)
        cunt1<=cunt1+1;
    else
        cunt1<=cunt1;
end


assign rd_en=(cunt_num==8)?1'b1:1'b0;
assign vled =(cunt_num==9&&cunt1<13)?1'b1:1'b0;
clk_wiz_0 u_clk(
    // Clock out ports
    .wr_clk(wr_clk),     // output wr_clk  100mhz
    .rd_clk(rd_clk),     // output rd_clk  125mhz
    // Status and control signals
    .reset(~rst_n), // input reset
    .locked(locked),       // output locked
   // Clock in ports
    .clk_in1(clk));      // input clk_in1


fifo_generator_0 u_fifo (
  .rst(~rst_n),                  // input wire rst
  .wr_clk(wr_clk),            // input wire wr_clk
  .rd_clk(rd_clk),            // input wire rd_clk
  .din(cunt),                  // input wire [7 : 0] din
  .wr_en(wr_en),              // input wire wr_en
  .rd_en(rd_en),              // input wire rd_en
  .dout(dout),                // output wire [7 : 0] dout
  .full(full),                // output wire full
  .empty(empty),              // output wire empty
  .wr_rst_busy(wr_rst_busy),  // output wire wr_rst_busy
  .rd_rst_busy(rd_rst_busy)  // output wire rd_rst_busy
);

uart_tx#(
    /*parameter*/ . CLK_DIV(125_000_000) ,
    /*parameter*/ . BIT    (9600) 
)u_tx(
    /*input       */ . clk  (rd_clk),
    /*input       */ . rst_n(rst_n),
    /*input       */ . vled (vled ),
    /*input  [7:0]*/ . data (dout ),
    /*output  reg */ . tx   (tx   ),
                     . busy (busy ) 
    );
endmodule
前面 dout初始值就是0 因为rd_en没有使能