module squence_check
(
input clk,
input rst_n,
input i_din,
output o_flg
)
//syte 1
//always @(posedge clk or negedge rst_n)
// if(!rst_n)
// dat_sequence <= 5'd0;
// else
// dat_sequence <= {dat_sequence3 : 0,i_din};
//
//assign flg = {dat_sequence3 : 0,i_din} == 5'b10010;
//
//always @(posedge clk or negedge rst_n)
// if(!rst_n)
// o_flg <= 1'd0;
// else
// o_flg <= flg;
//
always @(posedge clk or negedge rst_n)
if(!rst_n)
curr_state <= IDLE;
else
curr_state <= nxt_state;
always@ (*)
case(curr_state)
IDLE:
if(i_din == 1'd1)
nxt_state = S0;
else
nxt_state = IDLE;
S0:
if(i_din == 1'd0)
nxt_state = S1;
else
nxt_state = S0;
S1:
if(i_din == 1'd0)
nxt_state = S2;
else
nxt_state = S0;
S2:
if(i_din == 1'd1)
nxt_state = S3;
else
nxt_state = IDLE;
S3:
if(i_din == 1'd0)
nxt_state = S4;
else
nxt_state = S0;
S4:
if(i_din == 1'd0)
nxt_state = IDLE;
else
nxt_state = S0;
default:
nxt_state = IDLE;
endcase
assign o_flg = (curr_state == S4);
endmodule