Verilog Test Fixture 时钟激励

1、占空比50%时钟产生

always
begin
    <clock>    =    1'b0    ;
    #<PERIOD/2>    ;
    <clock>    =    1'b1    ;
    #<PERIOD/2>    ;
end

    reg <clock> = 1'b0    ;
    always
    begin
        #<PERIOD/2>    ;
        <clock>    =    ~<clock>    ;
    end    

2、高低电平参数时钟产生

always
begin
    <clock>    =    1'b0    ;
    #<LOW_TIME>    ;
    <clock>    =    1'b1    ;
    #<HIGH_TIME>    ;
end

3、占空比可调clk

always
begin
    <clock>    =    1'b0    ;
    #( <PERIOD> - (<PERIOD>*<DUTY_CYCLE>) )    ;
    <clock>    =    1'b1    ;
    #( <PERIOD> - <DUTY_CYCLE> )    ;
end    

4、差分时钟

always
begin
    clk_p    =    1'b0    ;
    clk_n    =    1'b1    ;
    #30    ;

    clk_p    =    1'b1    ;
    clk_n    =    1'b0    ;
    #30    ;
    
end