零门槛上手的RISC-V项目：nerv(附Verilog-vs-SysVerilog)

nerv这个项目同样是编写了Makefile的verilog项目，不过它的项目显示是用SystemVerilog而不是verilog，然而又又又没有用到SystemVerilog区别于verilog的特殊语法，比如logic变量，或者interface接口声明，或者interface接口中的modport，或者结构体struct及用于多个信号打包在一起类似于struct的pack，也也也没有区别于always@*的always_xxx这种增强的语法关键词，但文件名却是.sv文件。

还是基于老旧主机上的ubuntu22以及配套的iverilog, verilator, riscv64-unknown-elf-工具，看看能否做到零门槛上手。

chipcamp@chipcamp:~/src/riscv$ cat /etc/os-release ##ubuntu22系统@十年旧机器。

PRETTY_NAME="Ubuntu 22.04 LTS"

NAME="Ubuntu"

VERSION_ID="22.04"

VERSION ="22.04 (Jammy Jellyfish)"

VERSION_CODENAME=jammy

ID=ubuntu

ID_LIKE=debian

HOME_URL="https://www.ubuntu.com/"

SUPPORT_URL="https://help.ubuntu.com/"

BUG_REPORT_URL="https://bugs.launchpad.net/ubuntu/"

PRIVACY_POLICY_URL="https://www.ubuntu.com/legal/terms-and-policies/privacy-policy"

UBUNTU_CODENAME=jammy

chipcamp@chipcamp:~/src/riscv$ which iverilog

/usr/bin/iverilog

chipcamp@chipcamp:~/src/riscv$ which verilator

/usr/bin/ verilator

chipcamp@chipcamp:~/src/riscv$ which gtkwave

/usr/bin/gtkwave

chipcamp@chipcamp:~/src/riscv$ which riscv64-unknown-elf-gcc

/usr/bin/riscv64-unknown-elf-gcc

chipcamp@chipcamp:~/src/riscv$

chipcamp@chipcamp:~/src/riscv$ dpkg-query -S /usr/bin/iverilog /usr/bin/verilator /usr/bin/gtkwave /usr/bin/riscv64-unknown-elf-gcc

iverilog: /usr/bin/iverilog

verilator: /usr/bin/verilator

gtkwave: /usr/bin/gtkwave

gcc-riscv64-unknown-elf: /usr/bin/riscv64-unknown-elf-gcc

------以上所有的软件，都是使用apt-get install安装的，这是本文所说的"0依赖"。
------看看能不能零门槛体验，结果，在这个环境里失败了。如下所示。

chipcamp@chipcamp:~/src/riscv$ git clone https://gitcode.com/chipcamp/nerv.git

Cloning into 'nerv'...

remote: Enumerating objects: 615, done.

remote: Total 615 (delta 0), reused 0 (delta 0), pack-reused 615 (from 1)

Receiving objects: 100% (615/615), 3.85 MiB | 538.00 KiB/s, done.

Resolving deltas: 100% (387/387), done.

chipcamp@chipcamp:~/src/riscv$ cd nerv

chipcamp@chipcamp:~/src/riscv/nerv$ ls -la

total 184

drwxrwxr-x 6 chipcamp chipcamp 4096 Oct 7 12:39 .

drwxrwxr-x 5 chipcamp chipcamp 4096 Oct 7 12:39 ..

drwxrwxr-x 2 chipcamp chipcamp 4096 Oct 7 12:39 axi_cache

-rw-rw-r-- 1 chipcamp chipcamp 1849 Oct 7 12:39 cexdata.sh

-rw-rw-r-- 1 chipcamp chipcamp 2133 Oct 7 12:39 checks.cfg

-rw-rw-r-- 1 chipcamp chipcamp 853 Oct 7 12:39 COPYING

-rw-rw-r-- 1 chipcamp chipcamp 2190 Oct 7 12:39 disasm.py

drwxrwxr-x 2 chipcamp chipcamp 4096 Oct 7 12:39 docs

drwxrwxr-x 3 chipcamp chipcamp 4096 Oct 7 12:39 examples

-rw-rw-r-- 1 chipcamp chipcamp 1524 Oct 7 12:39 firmware.c

-rw-rw-r-- 1 chipcamp chipcamp 2178 Oct 7 12:39 firmware.s

drwxrwxr-x 8 chipcamp chipcamp 4096 Oct 7 12:39 .git

-rw-rw-r-- 1 chipcamp chipcamp 106 Oct 7 12:39 .gitignore

-rw-rw-r-- 1 chipcamp chipcamp 532 Oct 7 12:39 imemcheck.sby

-rw-rw-r-- 1 chipcamp chipcamp 2310 Oct 7 12:39 imemcheck.sv

-rw-rw-r-- 1 chipcamp chipcamp 1899 Oct 7 12:39 Makefile

-rw-rw-r-- 1 chipcamp chipcamp 24235 Oct 7 12:39 NERV.png

-rw-rw-r-- 1 chipcamp chipcamp 2339 Oct 7 12:39 nervsoc.sv

-rw-rw-r-- 1 chipcamp chipcamp 53665 Oct 7 12:39 nerv.sv

-rw-rw-r-- 1 chipcamp chipcamp 1173 Oct 7 12:39 README.md

-rw-rw-r-- 1 chipcamp chipcamp 2505 Oct 7 12:39 sections.lds

-rw-rw-r-- 1 chipcamp chipcamp 3269 Oct 7 12:39 testbench.gtkw

-rw-rw-r-- 1 chipcamp chipcamp 9733 Oct 7 12:39 testbench.sv

-rw-rw-r-- 1 chipcamp chipcamp 3918 Oct 7 12:39 trace.gtkw

-rw-rw-r-- 1 chipcamp chipcamp 3323 Oct 7 12:39 vectors.s

-rw-rw-r-- 1 chipcamp chipcamp 3883 Oct 7 12:39 wrapper.sv

chipcamp@chipcamp:~/src/riscv/nerv$ more Makefile

NERV -- Naive Educational RISC-V Processor

TOOLCHAIN_PREFIX?=riscv64-unknown-elf-

RISCV_ARCH?=rv32i(shell (TOOLCHAIN_PREFIX)as -march=rv32i_zicsr --dump-config 2>/dev/null && echo _zicsr)

test: firmware.hex testbench

vvp -N testbench +vcd

firmware.elf: firmware.s vectors.s firmware.c

(TOOLCHAIN_PREFIX)gcc -march=(RISCV_ARCH) -mabi=ilp32 -Os -Wall -Wextra -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o @ ^

firmware.hex: firmware.elf

(TOOLCHAIN_PREFIX)objcopy -O verilog < $@

testbench: testbench.sv nerv.sv

iverilog -g2012 -o testbench -D STALL -D NERV_DBGREGS testbench.sv nerv.sv

checks:

python3 ../../checks/genchecks.py

$(MAKE) -C checks

check: checks

bash cexdata.sh

cat cexdata/warnings.txt

cat cexdata/status.txt

show:

gtkwave testbench.vcd testbench.gtkw >> gtkwave.log 2>&1 &

trace:

gtkwave cexdata/checks_$(TRACE_CHECK)_ch0.vcd trace.gtkw >> gtkwave.log 2>&1 &

clean:

rm -rf firmware.elf firmware.hex testbench testbench.vcd gtkwave.log

rm -rf disasm.o disasm.s checks/ cexdata/

chipcamp@chipcamp:~/src/riscv/nerv$ make

riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -Os -Wall -Wextra -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf firmware.s vectors.s firmware.c

cc1: error: '-march=rv32i_zicsr': unsupported ISA subset 'z'

make: *** Makefile:26: firmware.elf Error 1

chipcamp@chipcamp:~/src/riscv/nerv$ riscv64-unknown-elf-gcc --version

riscv64-unknown-elf-gcc () 10.2.0

Copyright (C) 2020 Free Software Foundation, Inc.

This is free software; see the source for copying conditions. There is NO

warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

chipcamp@chipcamp:~/src/riscv/nerv$

换一个环境，是ubuntu24的LTS版本，则可以了。记录如下。

chipcamp@ChipCamp:~/src/temp$ git clone https://gitcode.com/chipcamp/nerv.git

Cloning into 'nerv'...

remote: Enumerating objects: 615, done.

remote: Total 615 (delta 0), reused 0 (delta 0), pack-reused 615 (from 1)

Receiving objects: 100% (615/615), 3.85 MiB | 697.00 KiB/s, done.

Resolving deltas: 100% (387/387), done.

chipcamp@ChipCamp:~/src/temp$ date

Wed Oct 7 13:13:25 CST 2026

chipcamp@ChipCamp:~/src/temp$ cd nerv

chipcamp@ChipCamp:~/src/temp/nerv$ ls -l

total 168

-rw-rw-r-- 1 chipcamp chipcamp 853 Oct 7 13:13 COPYING

-rw-rw-r-- 1 chipcamp chipcamp 1899 Oct 7 13:13 Makefile

-rw-rw-r-- 1 chipcamp chipcamp 24235 Oct 7 13:13 NERV.png

-rw-rw-r-- 1 chipcamp chipcamp 1173 Oct 7 13:13 README.md

drwxrwxr-x 2 chipcamp chipcamp 4096 Oct 7 13:13 axi_cache

-rw-rw-r-- 1 chipcamp chipcamp 1849 Oct 7 13:13 cexdata.sh

-rw-rw-r-- 1 chipcamp chipcamp 2133 Oct 7 13:13 checks.cfg

-rw-rw-r-- 1 chipcamp chipcamp 2190 Oct 7 13:13 disasm.py

drwxrwxr-x 2 chipcamp chipcamp 4096 Oct 7 13:13 docs

drwxrwxr-x 3 chipcamp chipcamp 4096 Oct 7 13:13 examples

-rw-rw-r-- 1 chipcamp chipcamp 1524 Oct 7 13:13 firmware.c

-rw-rw-r-- 1 chipcamp chipcamp 2178 Oct 7 13:13 firmware.s

-rw-rw-r-- 1 chipcamp chipcamp 532 Oct 7 13:13 imemcheck.sby

-rw-rw-r-- 1 chipcamp chipcamp 2310 Oct 7 13:13 imemcheck.sv

-rw-rw-r-- 1 chipcamp chipcamp 53665 Oct 7 13:13 nerv.sv

-rw-rw-r-- 1 chipcamp chipcamp 2339 Oct 7 13:13 nervsoc.sv

-rw-rw-r-- 1 chipcamp chipcamp 2505 Oct 7 13:13 sections.lds

-rw-rw-r-- 1 chipcamp chipcamp 3269 Oct 7 13:13 testbench.gtkw

-rw-rw-r-- 1 chipcamp chipcamp 9733 Oct 7 13:13 testbench.sv

-rw-rw-r-- 1 chipcamp chipcamp 3918 Oct 7 13:13 trace.gtkw

-rw-rw-r-- 1 chipcamp chipcamp 3323 Oct 7 13:13 vectors.s

-rw-rw-r-- 1 chipcamp chipcamp 3883 Oct 7 13:13 wrapper.sv

chipcamp@ChipCamp:~/src/temp/nerv$ make

riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -Os -Wall -Wextra -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf firmware.s vectors.s firmware.c

/usr/lib/gcc/riscv64-unknown-elf/13.2.0/../../../riscv64-unknown-elf/bin/ld: warning: firmware.elf has a LOAD segment with RWX permissions

riscv64-unknown-elf-objcopy -O verilog firmware.elf firmware.hex

iverilog -g2012 -o testbench -D STALL -D NERV_DBGREGS testbench.sv nerv.sv

nerv.sv:687: vvp.tgt sorry: Case unique/unique0 qualities are ignored.

vvp -N testbench +vcd

VCD info: dumpfile testbench.vcd opened for output.

Hello World!

Hello World again-----LUSimulated 889 cycles

testbench.sv:249: $finish called at 8900 (1s)

chipcamp@ChipCamp:~/src/temp/nerv$ /usr/bin/riscv64-unknown-elf-gcc --version

riscv64-unknown-elf-gcc (13.2.0-11ubuntu1+12) 13.2.0

Copyright (C) 2023 Free Software Foundation, Inc.

This is free software; see the source for copying conditions. There is NO

warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

chipcamp@ChipCamp:~/src/temp/nerv$ cat /etc/os-release

PRETTY_NAME="Ubuntu 24.04.3 LTS"

NAME="Ubuntu"

VERSION_ID="24.04"

VERSION="24.04.3 LTS (Noble Numbat)"

VERSION_CODENAME=noble

ID=ubuntu

ID_LIKE=debian

HOME_URL="https://www.ubuntu.com/"

SUPPORT_URL="https://help.ubuntu.com/"

BUG_REPORT_URL="https://bugs.launchpad.net/ubuntu/"

PRIVACY_POLICY_URL="https://www.ubuntu.com/legal/terms-and-policies/privacy-policy"

UBUNTU_CODENAME=noble

LOGO=ubuntu-logo

chipcamp@ChipCamp:~/src/temp/nerv$

----可以看出，nerv项目在Ubuntu24.04 LTS版本及配套的riscv64-unknown-elf-gcc 13.2.0下，是一键Make运行的。

----考虑到现在的时间点，Ubuntu24.04LTS不算很老，因此nerv仍然可以认为是零门槛体验的。

----顺便看一下上一个例子darkriscv的make all失败在riscv64-unknown-elf-gcc编译过程中，看看在Ubuntu24.04 LTS with riscv-gcc-13.2是否还存在。如下。

chipcamp@ChipCamp:~/src/temp/nerv$ /usr/bin/riscv64-unknown-elf-gcc --version

riscv64-unknown-elf-gcc (13.2.0-11ubuntu1+12) 13.2.0

Copyright (C) 2023 Free Software Foundation, Inc.

This is free software; see the source for copying conditions. There is NO

warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

chipcamp@ChipCamp:~/src/temp/nerv$ cat /etc/os-release

PRETTY_NAME="Ubuntu 24.04.3 LTS"

NAME="Ubuntu"

VERSION_ID="24.04"

VERSION="24.04.3 LTS (Noble Numbat)"

VERSION_CODENAME=noble

ID=ubuntu

ID_LIKE=debian

HOME_URL="https://www.ubuntu.com/"

SUPPORT_URL="https://help.ubuntu.com/"

BUG_REPORT_URL="https://bugs.launchpad.net/ubuntu/"

PRIVACY_POLICY_URL="https://www.ubuntu.com/legal/terms-and-policies/privacy-policy"

UBUNTU_CODENAME=noble

LOGO=ubuntu-logo

chipcamp@ChipCamp:~/src/temp/nerv cd .. chipcamp@ChipCamp:\~/src/temp git clone https://gitcode.com/chipcamp/darkriscv.git

Cloning into 'darkriscv'...

remote: Enumerating objects: 3796, done.

remote: Total 3796 (delta 0), reused 0 (delta 0), pack-reused 3796 (from 1)

Receiving objects: 100% (3796/3796), 4.96 MiB | 698.00 KiB/s, done.

Resolving deltas: 100% (2536/2536), done.

chipcamp@ChipCamp:~/src/temp$ cd darkriscv

chipcamp@ChipCamp:~/src/temp/darkriscv$ make all

make -C src all

make1: Entering directory '/home/chipcamp/src/temp/darkriscv/src'

/usr/bin/riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mlittle-endian -c -o boot.o boot.S

/usr/bin/riscv64-unknown-elf-cpp -P -DMLEN=(awk '/define MLEN/ { print 2\*\*3 }' ../rtl/config.vh) darksocv.lds darksocv.ld

make -C darkshell all

make2: Entering directory '/home/chipcamp/src/temp/darkriscv/src/darkshell'

/usr/bin/riscv64-unknown-elf-gcc -Wall -fcommon -ffreestanding -Os -fno-delete-null-pointer-checks -mlittle-endian -march=rv32i_zicsr -mabi=ilp32 -Idarklibc/include -I../darklibc/include -D__RISCV__ -DBUILD="\"Wed, 07 Oct 2026 13:36:01 +0800\"" -DARCH="\"rv32i_zicsr\"" -mno-div -mcmodel=medany -S main.c -o main.s

/usr/bin/riscv64-unknown-elf-as -march=rv32i_zicsr -mabi=ilp32 -mlittle-endian -c main.s -o main.o

/usr/bin/riscv64-unknown-elf-ar -rcs darkshell.a main.o

/usr/bin/riscv64-unknown-elf-ranlib darkshell.a

sources ok for darkshell.a.

make2: Leaving directory '/home/chipcamp/src/temp/darkriscv/src/darkshell'

make -C darklibc all

make2: Entering directory '/home/chipcamp/src/temp/darkriscv/src/darklibc'

/usr/bin/riscv64-unknown-elf-gcc -Wall -fcommon -ffreestanding -Os -fno-delete-null-pointer-checks -mlittle-endian -march=rv32i_zicsr -mabi=ilp32 -Idarklibc/include -I../darklibc/include -D__RISCV__ -DBUILD="\"Wed, 07 Oct 2026 13:36:01 +0800\"" -DARCH="\"rv32i_zicsr\"" -mno-div -mcmodel=medany -Iinclude -S stdio.c -o stdio.s

/usr/bin/riscv64-unknown-elf-gcc -Wall -fcommon -ffreestanding -Os -fno-delete-null-pointer-checks -mlittle-endian -march=rv32i_zicsr -mabi=ilp32 -Idarklibc/include -I../darklibc/include -D__RISCV__ -DBUILD="\"Wed, 07 Oct 2026 13:36:01 +0800\"" -DARCH="\"rv32i_zicsr\"" -mno-div -mcmodel=medany -Iinclude -S io.c -o io.s

/usr/bin/riscv64-unknown-elf-gcc -Wall -fcommon -ffreestanding -Os -fno-delete-null-pointer-checks -mlittle-endian -march=rv32i_zicsr -mabi=ilp32 -Idarklibc/include -I../darklibc/include -D__RISCV__ -DBUILD="\"Wed, 07 Oct 2026 13:36:01 +0800\"" -DARCH="\"rv32i_zicsr\"" -mno-div -mcmodel=medany -Iinclude -S string.c -o string.s

/usr/bin/riscv64-unknown-elf-gcc -Wall -fcommon -ffreestanding -Os -fno-delete-null-pointer-checks -mlittle-endian -march=rv32i_zicsr -mabi=ilp32 -Idarklibc/include -I../darklibc/include -D__RISCV__ -DBUILD="\"Wed, 07 Oct 2026 13:36:01 +0800\"" -DARCH="\"rv32i_zicsr\"" -mno-div -mcmodel=medany -Iinclude -S misc.c -o misc.s

/usr/bin/riscv64-unknown-elf-gcc -Wall -fcommon -ffreestanding -Os -fno-delete-null-pointer-checks -mlittle-endian -march=rv32i_zicsr -mabi=ilp32 -Idarklibc/include -I../darklibc/include -D__RISCV__ -DBUILD="\"Wed, 07 Oct 2026 13:36:01 +0800\"" -DARCH="\"rv32i_zicsr\"" -mno-div -mcmodel=medany -Iinclude -S unistd.c -o unistd.s

/usr/bin/riscv64-unknown-elf-as -march=rv32i_zicsr -mabi=ilp32 -mlittle-endian -c stdio.s -o stdio.o

/usr/bin/riscv64-unknown-elf-as -march=rv32i_zicsr -mabi=ilp32 -mlittle-endian -c io.s -o io.o

/usr/bin/riscv64-unknown-elf-as -march=rv32i_zicsr -mabi=ilp32 -mlittle-endian -c string.s -o string.o

/usr/bin/riscv64-unknown-elf-as -march=rv32i_zicsr -mabi=ilp32 -mlittle-endian -c misc.s -o misc.o

/usr/bin/riscv64-unknown-elf-as -march=rv32i_zicsr -mabi=ilp32 -mlittle-endian -c unistd.s -o unistd.o

/usr/bin/riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mlittle-endian -c -o util.o util.S

/usr/bin/riscv64-unknown-elf-ar -rcs darklibc.a stdio.o io.o string.o misc.o unistd.o util.o

/usr/bin/riscv64-unknown-elf-ranlib darklibc.a

sources ok for darklibc.a.

make2: Leaving directory '/home/chipcamp/src/temp/darkriscv/src/darklibc'

#/usr/bin/riscv64-unknown-elf-ranlib darkshell/darkshell.a darklibc/darklibc.a

/usr/bin/riscv64-unknown-elf-ld -Tdarksocv.ld -Map=darksocv.map -m elf32lriscv -static -gc-sections --entry=_start -o darksocv.o boot.o darkshell/darkshell.a darklibc/darklibc.a

/usr/bin/riscv64-unknown-elf-ld: warning: darksocv.o has a LOAD segment with RWX permissions

/usr/bin/riscv64-unknown-elf-objdump -D darksocv.o > darksocv.S

/usr/bin/riscv64-unknown-elf-objcopy -O binary darksocv.o darksocv.bin

hexdump -ve '1/4 "%08x\n"' darksocv.bin > darksocv.mem

dd if=darksocv.bin of=darksocv_uart.bin skip=512 bs=1

7440+0 records in

7440+0 records out

7440 bytes (7.4 kB, 7.3 KiB) copied, 0.00403438 s, 1.8 MB/s

rm darksocv.bin

uncomment for MIF file

#awk 'BEGIN { print "DEPTH = 1024;\nWIDTH = 32;\nADDRESS_RADIX = HEX;\nDATA_RADIX = HEX;\nCONTENT\nBEGIN" } { printf("%08x : %s\n",NR-1,); } END { print "END;" }' < darksocv.mem > darksocv.mif

wc -l darksocv.mem

1988 darksocv.mem

mem ok for little-endian.

echo build is ok for darksocv.mem

build is ok for darksocv.mem

make1: Leaving directory '/home/chipcamp/src/temp/darkriscv/src'

make -C sim all

make1: Entering directory '/home/chipcamp/src/temp/darkriscv/sim'

iverilog -Wall -I ../rtl -o darksocv darksimv.v ../rtl/darksocv.v ../rtl/darkbridge.v ../rtl/darkuart.v ../rtl/darkriscv.v ../rtl/darkpll.v ../rtl/darkram.v ../rtl/darkio.v ../rtl/darkcache.v ../rtl/darkmac.v ../rtl/lib/sdram/mt48lc16m16a2_ctrl.v

echo "VCDS=darksocv.vcd: XSIM=darksocv"

VCDS=darksocv.vcd: XSIM=darksocv

dpram: unified BRAM w/ 2048x32-bit

WARNING: ../rtl/darkram.v:88: $readmemh(../src/darksocv.mem): Not enough words in the file for the requested range 0:2047.

VCD info: dumpfile darksocv.vcd opened for output.

reset (startup)

sdram: CLK: 64 MHz

sdram: WAIT_100US: 6400 cycles

sdram: TRP: 2 cycles

sdram: TRC: 5 cycles

sdram: TRCD: 2 cycles

sdram: TCH: 1 cycles

sdram: CAS_LATENCY: 2 cycles

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv

vvvvvvvvvvvvvvvvvvvvvvvvvvvv

rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv

rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv

rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv

rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv

rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv

rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv

rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv

rr vvvvvvvvvvvvvvvvvvvvvv

rr vvvvvvvvvvvvvvvvvvvvvvvv rr

rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr

rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr

rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr

rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr

rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr

rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr

rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr

rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr

rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr

rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr

INSTRUCTION SETS WANT TO BE FREE

boot0: main@0200 stack@1f7c

board: simulation only (id=0)

build: Wed, 07 Oct 2026 13:36:01 +0800 for rv32i_zicsr

core0: darkriscv@100MHz rv32i little-endian

bram0: text@0200+1418 data@1618+08f8 stack@2000

bram0: 240 bytes free

uart0: 115.2kbps (div=25603)

timr0: 1000Hz (div=99999)

csrxx: not found

stvec: not found

mtvec: not found (polling)

Welcome to DarkRISCV!

495> ^C

** VVP Stop(0) **

** Flushing output streams.

** Current simulation time is 509455000 ticks.

> finish

** Continue **

make1: *** Makefile:98: darksocv.vcd Interrupt

make: *** Makefile:47: all Interrupt

chipcamp@ChipCamp:~/src/temp/darkriscv$

----没有问题。改用Ubuntu 24.04 LTS系统，配套的riscv64-unknown-elf-gcc则是13.2版本，darkriscv项目的firmware.hex就可以正常编译了，在Ubuntu 22.04 LTS版本下gcc版本低而出现的-mlittle-endian选项不支持的问题消失了。

<<<<<<<<完END>>>>>>>>

关键词：nerv, riscv64-unknown-elf-gcc, systemverilog, interface, modport, pack, struct, always_ff。

摘要：本文记录了开源RISC-V项目nerv的make体验过程。在Ubuntu 22.04 LTS所配套的riscv-gcc-10.x版本不支持-mlittle-entian而build失败的问题，在Ubuntu 24.04 LTS所配套的riscv-gcc-13.2版本则没有问题。这个nerv项目虽然以.sv文件标示SystemVerilog语言，但实际上它没有使用SystemVerilog相对Verilog语言的任何主要语法如interface，modport，pack，struct，always_ff等。

附送：Verilog vs SystemVerilog Summary。

<<<<<<<<END of 附录>>>>>>>>