[HDLBits] Mt2015 muxdff

Taken from ECE253 2015 midterm question 5

Consider the sequential circuit below:

Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a flip-flop and multiplexer in it. Write a Verilog module (containing one flip-flop and multiplexer) named top_module for this submodule.

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
	wire D;
    assign D = L ? r_in : q_in;
    always@(posedge clk) Q<=D;
endmodule

这里体现出来，必须分开分步写各个器件。