Fsm ps2

The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it's not obvious where messages start and end. The only indication is that the first byte of each three byte message always has bit[3]=1 (but bit[3] of the other two bytes may be 1 or 0 depending on data).

We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with bit[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done).

The FSM should signal done in the cycle immediately after the third byte of each message was successfully received

cpp 复制代码
module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //

    parameter BYTE1 = 2'b00,
    			BYTE2 = 2'b01,
    		BYTE3 = 2'b11,
    		DONE = 2'b10;
    
    reg [1:0] state;
    reg [1:0] next_state;
    
   
    // State transition logic (combinational)
    always@(*)
        case(state)
        	BYTE1: 
                if(in[3])
                    next_state <= BYTE2;
            	else 
                     next_state <= BYTE1;
            BYTE2:  
                     next_state <= BYTE3;
            BYTE3:  
                    next_state <= DONE; 
            DONE: 
                if(in[3])
                    next_state <= BYTE2;
            	else 
                     next_state <= BYTE1;
            default:
                next_state <= BYTE1;
        endcase
    
    // State flip-flops (sequential)
    always@(posedge clk)
        if(reset)
        	state <= BYTE1;
    	else 
            state <= next_state;
    // Output logic
	assign done = state == DONE;
    
endmodule
相关推荐
FPGA小迷弟7 小时前
京微齐力FPGA联合modelsim仿真操作
fpga开发·ic·verilog·fpga·仿真
FPGA_小田老师1 天前
FPGA例程(3):按键检测实验
fpga开发·verilog·vivado·led灯·按键测试
FPGA小迷弟4 天前
modelsim使用教程,仿真技巧,精华帖
fpga开发·verilog·fpga·modelsim
才鲸嵌入式12 天前
香山CPU(国产开源)的 SoC SDK底层程序编写,以及其它开源SoC芯片介绍
c语言·单片机·嵌入式·arm·cpu·verilog·fpga
莫问前程_满城风雨14 天前
verilog 可变范围的bit选择
运维·服务器·verilog
啄缘之间15 天前
10.基于 MARCH C+ 算法的SRAM BIST
经验分享·笔记·学习·verilog
s090713616 天前
FPGA中同步与异步复位
fpga开发·verilog·xilinx·zynq
民乐团扒谱机16 天前
十字路口交通信号灯控制器设计(Multisim 电路 + Vivado 仿真)
单片机·fpga开发·verilog·状态机·仿真·时序逻辑·multism
9527华安1 个月前
FPGA纯verilog实现JESD204B协议,基于ADRV9009数据环回收发,提供2套工程源码和技术支持
fpga开发·verilog·jesd204b·adrv9009
刀法自然1 个月前
verilog实现n分频,n为奇数
fpga开发·verilog·分频器