Fsm ps2

The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it's not obvious where messages start and end. The only indication is that the first byte of each three byte message always has bit3=1 (but bit3 of the other two bytes may be 1 or 0 depending on data).

We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with bit3=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done).

The FSM should signal done in the cycle immediately after the third byte of each message was successfully received

cpp 复制代码
module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //

    parameter BYTE1 = 2'b00,
    			BYTE2 = 2'b01,
    		BYTE3 = 2'b11,
    		DONE = 2'b10;
    
    reg [1:0] state;
    reg [1:0] next_state;
    
   
    // State transition logic (combinational)
    always@(*)
        case(state)
        	BYTE1: 
                if(in[3])
                    next_state <= BYTE2;
            	else 
                     next_state <= BYTE1;
            BYTE2:  
                     next_state <= BYTE3;
            BYTE3:  
                    next_state <= DONE; 
            DONE: 
                if(in[3])
                    next_state <= BYTE2;
            	else 
                     next_state <= BYTE1;
            default:
                next_state <= BYTE1;
        endcase
    
    // State flip-flops (sequential)
    always@(posedge clk)
        if(reset)
        	state <= BYTE1;
    	else 
            state <= next_state;
    // Output logic
	assign done = state == DONE;
    
endmodule
相关推荐
学习FPGA的电气小兴兴3 天前
基于FPGA的CORDIC旋转模式实现sin和cos运算
fpga开发·信号处理·数字信号处理·verilog·fpga·verilog hdl·cordic
FPGA开源工坊10 天前
ISP图像处理--Bayer Raw格式
图像处理·人工智能·verilog·fpga·isp
qq_1508419911 天前
用verilog语言在Quartus Prime Lite 18中对CPLD EPM570T100C5进行编程
verilog·quartus·cpld
芯路行者25 天前
4.4 HDLBits —— 更多时序逻辑电路
fpga开发·verilog·fpga·hdlbits
芯路行者1 个月前
7 HDLBits —— 验证:编写测试激励文件
fpga开发·verilog·fpga·hdlbits
芯路行者1 个月前
4.1 HDLBits —— 时序逻辑电路之锁存器与触发器
fpga开发·verilog·fpga·hdlbits
芯路行者1 个月前
5 HDLBits —— 构建更大的电路
fpga开发·verilog·fpga·hdlbits
芯路行者1 个月前
4.3 HDLBits —— 时序逻辑电路之移位寄存器
fpga开发·verilog·fpga·hdlbits
芯路行者1 个月前
4.2 HDLBits —— 时序逻辑电路之计数器
fpga开发·verilog·fpga·hdlbits
鬼手点金1 个月前
FPGA常用型号参考
fpga开发·verilog·vivado·xilinx·vhdl·altera·lattice