Fsm ps2

The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it's not obvious where messages start and end. The only indication is that the first byte of each three byte message always has bit[3]=1 (but bit[3] of the other two bytes may be 1 or 0 depending on data).

We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with bit[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done).

The FSM should signal done in the cycle immediately after the third byte of each message was successfully received

cpp 复制代码
module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //

    parameter BYTE1 = 2'b00,
    			BYTE2 = 2'b01,
    		BYTE3 = 2'b11,
    		DONE = 2'b10;
    
    reg [1:0] state;
    reg [1:0] next_state;
    
   
    // State transition logic (combinational)
    always@(*)
        case(state)
        	BYTE1: 
                if(in[3])
                    next_state <= BYTE2;
            	else 
                     next_state <= BYTE1;
            BYTE2:  
                     next_state <= BYTE3;
            BYTE3:  
                    next_state <= DONE; 
            DONE: 
                if(in[3])
                    next_state <= BYTE2;
            	else 
                     next_state <= BYTE1;
            default:
                next_state <= BYTE1;
        endcase
    
    // State flip-flops (sequential)
    always@(posedge clk)
        if(reset)
        	state <= BYTE1;
    	else 
            state <= next_state;
    // Output logic
	assign done = state == DONE;
    
endmodule
相关推荐
可编程芯片开发8 天前
基于FPGA的PID控制器verilog实现,包含simulink对比模型
fpga开发·verilog·simulink·pid控制器
__pop_17 天前
SV 仿真的常识
verilog
nanxl120 天前
FPGA-DDS信号发生器
fpga开发·verilog·vivado
nanxl120 天前
FPGA-数字时钟
fpga开发·verilog·vivado
__pop_25 天前
system verilog 语句 耗时规则
verilog
0基础学习者1 个月前
按键消抖(用状态机实现)
前端·笔记·fpga开发·verilog·fpga
浮梦终焉1 个月前
VS Code下开发FPGA——FPGA开发体验提升__下
ide·fpga开发·verilog·vs code
迎风打盹儿1 个月前
FPGA同步复位、异步复位、异步复位同步释放仿真
verilog·fpga·vivado·复位
肯德基疯狂星期四-V我501 个月前
【FPGA】状态机思想实现LED流水灯&HDLbits组合逻辑题训练
fpga开发·verilog·de2-115
可编程芯片开发1 个月前
基于FPGA的特定序列检测器verilog实现,包含testbench和开发板硬件测试
fpga开发·verilog·特定序列检测