Lemmings2

See also: Lemmings1.

In addition to walking left and right, Lemmings will fall (and presumably go "aaah!") if the ground disappears underneath them.

In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say "aaah!". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.

Build a finite state machine that models this behaviour.

clkbump_leftbump_rightgroundwalk_leftwalk_rightaaah

See also: Lemmings3 and Lemmings4.

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
	parameter LEFT=0, RIGHT=1,FALLL=2,FALLR=3;
    //fall分出左右更有利于编程
    reg [1:0]state, next_state;
	//这里两位状态寄存器,必须记住!
    always @(*) begin
        // State transition logic
        case(state)
            LEFT:next_state<=ground?(bump_left?RIGHT:LEFT):FALLL;
            RIGHT:next_state<=ground?(bump_right?LEFT:RIGHT):FALLR;
            //这里要记得ground判定在前
            FALLL:next_state<=ground?LEFT:FALLL;
            FALLR:next_state<=ground?RIGHT:FALLR;
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)
            state<=LEFT;
        else
            state<=next_state;
    end

    // Output logic
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah=(state==FALLL||state==FALLR);
endmodule

fall分出左右是点睛之笔

相关推荐
可知可知不可知3 小时前
明解FPGA中LUT原理
fpga开发
如何学会学习?5 小时前
3. FPGA内部存储资源
fpga开发
szxinmai主板定制专家5 小时前
【国产NI替代】基于A7 FPGA+AI的16振动(16bits)终端PCIE数据采集板卡
人工智能·fpga开发
stm 学习ing5 小时前
HDLBits训练6
经验分享·笔记·fpga开发·fpga·eda·verilog hdl·vhdl
szxinmai主板定制专家6 小时前
【NI国产替代】基于国产FPGA+全志T3的全国产16振动+2转速(24bits)高精度终端采集板卡
人工智能·fpga开发
stm 学习ing6 小时前
HDLBits训练4
经验分享·笔记·fpga开发·课程设计·fpga·eda·verilog hdl
cckkppll6 小时前
判断实例化或推断的时机
fpga开发
博览鸿蒙7 小时前
选择FPGA开发,学历是硬性要求吗?
fpga开发
周湘zx1 天前
项目三:信号源的FPGA实现
fpga开发
9527华安1 天前
FPGA多路MIPI转FPD-Link视频缩放拼接显示,基于IMX327+FPD953架构,提供2套工程源码和技术支持
fpga开发·架构·音视频