Lemmings2

See also: Lemmings1.

In addition to walking left and right, Lemmings will fall (and presumably go "aaah!") if the ground disappears underneath them.

In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say "aaah!". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.

Build a finite state machine that models this behaviour.

clkbump_leftbump_rightgroundwalk_leftwalk_rightaaah

See also: Lemmings3 and Lemmings4.

复制代码
module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
	parameter LEFT=0, RIGHT=1,FALLL=2,FALLR=3;
    //fall分出左右更有利于编程
    reg [1:0]state, next_state;
	//这里两位状态寄存器,必须记住!
    always @(*) begin
        // State transition logic
        case(state)
            LEFT:next_state<=ground?(bump_left?RIGHT:LEFT):FALLL;
            RIGHT:next_state<=ground?(bump_right?LEFT:RIGHT):FALLR;
            //这里要记得ground判定在前
            FALLL:next_state<=ground?LEFT:FALLL;
            FALLR:next_state<=ground?RIGHT:FALLR;
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)
            state<=LEFT;
        else
            state<=next_state;
    end

    // Output logic
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah=(state==FALLL||state==FALLR);
endmodule

fall分出左右是点睛之笔

相关推荐
ShiMetaPi11 小时前
操作【GM3568JHF】FPGA+ARM异构开发板 使用指南:蓝牙
arm开发·嵌入式硬件·fpga开发·rk3568
知识充实人生19 小时前
静态时序分析详解之时序路径类型
fpga开发·时序路径·关键路径
9527华安2 天前
Xilinx系列FPGA实现DP1.4视频收发,支持4K60帧分辨率,提供2套工程源码和技术支持
fpga开发·音视频·dp1.4·4k60帧
cycf2 天前
高速接口基础
fpga开发
forgeda2 天前
从Vivado集成Lint功能,看FPGA设计的日益ASIC化趋势
fpga开发·vivado·lint·eco·静态检查功能
hexiaoyan8272 天前
国产化FPGA开发板:2050-基于JFMK50T4(XC7A50T)的核心板
fpga开发·工业图像输出·vc709e板卡·zynq 通用计算平台·模拟型号处理
m0_575046342 天前
FPGA数据流分析
数据分析·fpga·数据流分析
雨洛lhw2 天前
The Xilinx 7 series FPGAs 设计PCB 该选择绑定哪个bank引脚,约束引脚时如何定义引脚电平标准?
fpga开发·bank·电平标准
红糖果仁沙琪玛3 天前
FPGA ad9248驱动
fpga开发
forgeda3 天前
半年报中的FPGA江湖:你打你的,我打我的
fpga·行业现状·竞争格局