keyscan_tb

`timescale 1ns/1ps

module Rom_tb;

reg clk;

reg rst_n;

reg [4:0] num;

reg [3:0] row;

wire [3:0] col;

wire [7:0] q;

initial begin

clk <= 1'b1;

rst_n <= 1'b0;

#20 rst_n <= 1'b1;

#100 num <= 5'h1;

#500 num <= 5'h1F;

#10000 num <= 5'h2;

#500 num <= 5'h1F;

#10000 num <= 5'h3;

#500 num <= 5'h1F;

#10000 num <= 5'h4;

#500 num <= 5'h1F;

end

always #5 clk = !clk;

Rom RomInst(

.clk (clk),

.rst_n (rst_n),

.row (row),

.col (col),

.q (q)

);

always @ (*)

begin

case (num)

5'h0: row <= {1'b1, 1'b1, 1'b1, col[0]};

5'h1: row <= {1'b1, 1'b1, 1'b1, col[1]};

5'h2: row <= {1'b1, 1'b1, 1'b1, col[2]};

5'h3: row <= {1'b1, 1'b1, 1'b1, col[3]};

5'h4: row <= {1'b1, 1'b1, col[0], 1'b1};

5'h5: row <= {1'b1, 1'b1, col[1], 1'b1};

5'h6: row <= {1'b1, 1'b1, col[2], 1'b1};

5'h7: row <= {1'b1, 1'b1, col[3], 1'b1};

5'h8: row <= {1'b1, col[0], 1'b1, 1'b1};

5'h9: row <= {1'b1, col[1], 1'b1, 1'b1};

5'hA: row <= {1'b1, col[2], 1'b1, 1'b1};

5'hB: row <= {1'b1, col[3], 1'b1, 1'b1};

5'hC: row <= {col[0], 1'b1, 1'b1, 1'b1};

5'hD: row <= {col[1], 1'b1, 1'b1, 1'b1};

5'hE: row <= {col[2], 1'b1, 1'b1, 1'b1};

5'hF: row <= {col[2], 1'b1, 1'b1, 1'b1};

default: row <= {1'b1, 1'b1, 1'b1, 1'b1};

endcase

end

defparam RomInst.KeyScanInst.T10ms = 5;

endmodule

相关推荐
ZYNQRFSOC10 小时前
基于XCKU5P纯逻辑 NVME测试
fpga开发
FPGA小迷弟14 小时前
使用FPGA开发高速AD/DA芯片的接口学习
fpga开发
stars-he16 小时前
FPGA学习笔记(6)逻辑设计小结与以太网发送前置
笔记·学习·fpga开发
燎原星火*16 小时前
FPGA 逻辑级数
fpga开发
175063319451 天前
Vivado Zynq7020 生成正弦波(查表法) + 行为级仿真
fpga开发
Terasic友晶科技1 天前
4-DE10-Nano的HDMI方块移动案例——I2C通信协议
fpga开发·i2c·hdmi·de10-nano·i2c通信协议
云雾J视界2 天前
FPGA在AI时代的角色重塑:硬件可重构性与异构计算的完美结合
fpga开发·边缘计算·gpu·vitis·ai推理·azure云·异构编程
s09071363 天前
FPGA中CIC设计注意事项
算法·fpga开发·cic滤波器
Aaron15883 天前
RFSOC+VU13P在无线信道模拟中的技术应用分析
数据结构·人工智能·算法·fpga开发·硬件架构·硬件工程·射频工程
碎碎思3 天前
BerkeleyLab Bedrock:为 FPGA 与加速计算打造的开源基石
fpga开发·开源