闩锁
Vivado日志文件报告已识别闩锁的类型和大小。
推断锁存通常是HDL编码错误的结果，例如不完整的if或case声明。
Vivado synthesis针对以下报告示例中显示的实例发出警告。此警告允许您验证推断的Latch功能是否为预期功能。
Latches Reporting Example
* Vivado.log *
WARNING: Synth 8-327 inferring latch for variable 'Q_reg'
Report Cell Usage:
-----+----+-----
|Cell|Count
-----+----+-----
2 |LD | 1
-----+----+-----
Latch With Positive Gate and Asynchronous Reset
Coding Verilog Example
Filename: latches.v
// Latch with Positive Gate and Asynchronous Reset
// File: latches.v
module latches (
input G,
input D,
input CLR,
output reg Q
);
always @ *
begin
if(CLR)
Q = 0;
else if(G)
Q = D;
end
endmodule
Latch With Positive Gate and Asynchronous Reset
Coding VHDL Example
Filename: latches.vhd
-- Latch with Positive Gate and Asynchronous Reset
-- File: latches.vhd
library ieee;
use ieee.std_logic_1164.all;
entity latches is
port(
G, D, CLR : in std_logic;
Q : out std_logic
);
end latches;
architecture archi of latches is
begin
process(CLR, D, G)
begin
if (CLR = '1') then
Q <= '0';
elsif (G = '1') then
Q <= D;
end if;
end process;
end archi;
•三态缓冲器通常由信号或if-else结构建模。
•这适用于缓冲器驱动板上的内部总线还是外部总线设备所在的位置。
•在if-else的一个分支中，信号被分配了一个高阻抗值。下载编码示例中的编码示例文件。
三态实现
当驱动下列的
•电路的外部引脚（OBUFT）
•内部总线（BUFT）：
○ 推断出的BUFT通过Vivado合成自动转换为LUT中实现的逻辑。
○ 当推断BUFT的内部总线驱动顶部模块的输出时，Vivado合成推断出OBUF。
三态报告示例
在合成过程中推断并报告三态缓冲液。
* Vivado log file *
Report Cell Usage:
-----+-----+-----
|Cell |Count
-----+-----+-----
1 |OBUFT| 1
-----+-----+-----
Tristate Description Using Concurrent Assignment Coding Verilog
Example
Filename: tristates_2.v
// Tristate Description Using Concurrent Assignment
// File: tristates_2.v
//
module tristates_2 (T, I, O);
input T, I;
output O;
assign O = (~T) ? I: 1'bZ;
endmodule
Tristate Description Using Combinatorial Process Implemented
with OBUFT Coding VHDL Example
Filename: tristates_1.vhd
-- Tristate Description Using Combinatorial Process
-- Implemented with an OBUFT (IO buffer)
-- File: tristates_1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity tristates_1 is
port(
T : in std_logic;
I : in std_logic;
O : out std_logic
);
end tristates_1;
architecture archi of tristates_1 is
begin
process(I, T)
begin
if (T = '0') then
O <= I;
else
O <= 'Z';
end if;
end process;
end archi;
Tristate Description Using Combinatorial Always Block Coding
Verilog Example
Filename: tristates_1.v
// Tristate Description Using Combinatorial Always Block
// File: tristates_1.v
//
module tristates_1 (T, I, O);
input T, I;
output O;
reg O;
always @(T or I)
begin
if (~T)
O = I;
else
O = 1'bZ;
end
endmodule