Circuits--Sequential--Registers_2

1. 3-bit LFSR

   module top_module (
   input [2:0] SW, // R
   input [1:0] KEY, // L and clk
   output [2:0] LEDR); // Q

    wire clk = KEY[0];
    always @(posedge clk)
        begin
            case(KEY[1])
                1'b0:	
                    begin
                        LEDR[0]<=LEDR[2];
                        LEDR[1]<=LEDR[0];
                        LEDR[2]<=LEDR[1]^LEDR[2];
                    end
                1'b1:	
                    begin
                        LEDR[0]<=SW[0];
                        LEDR[1]<=SW[1];
                        LEDR[2]<=SW[2];
                    end
            endcase
        end

   endmodule

2. 32-bit LFSR

   module top_module(
   input clk,
   input reset, // Active-high synchronous reset to 32'h1
   output [31:0] q
   );

    integer i;
    always@(posedge clk)
        begin
            if(reset)
                q<=32'h1;
            else
                begin
                    for(i=0;i<32;i++)
                        begin
                            if(i==0||i==1||i==21) 
                                q[i]<=q[i+1]^q[0];
                            else if(i==31)
                                q[31]<=q[0]^1'b0;
                            else
                                q[i]<=q[i+1];
                        end
                    
                end
            
        end

   endmodule

3.shift register

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    
    reg [3:0] q;
    
    assign out = q[3];
    always@(posedge clk)
        begin
            if(!resetn)
                q<=0;
            else
                begin                 
                    q<={q[2:0],in};                       
                end
        end
endmodule