FPGA PCIe加载提速方案

目录

1.bit流压缩

2.flash加载速度

3.Tandem模式


1.bit流压缩

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

2.flash加载速度

打开bitstream setting,设置SPI的线宽和速率(线宽按原理图设置,速率尽可能高)

3.Tandem模式

Overview

PCIe requires a link training within 120ms after power is stable. This can be a challenging phase of programming FPGA devices due to the size of the bitstream to program the FPGA and the rate of configuration available. Therefore, the Tandem PCIe feature is used to address this challenge.

The Tandem PCIe contains two stages of bitstream. The first stage includes the programming of the necessary memory cells for the PCIe loaded from the Programmable Read Only Memory (PROM). Afterwards, the PCIe port is capable of handling and responding to enumerations. In parallel, the second stage bitstream is transmitted via the PCIe link. The second stage bitstream contains the user application that can be configured using the Media Configuration Access Port (MCAP). Please refer to (Answer Record 64761).

See the figure below for the load steps.

Figure 1 - Tandem PCIe Bitstream Load Steps

This blog provides a step-by-step guide on how to use the Tandem PCIe feature on a KCU116 board.

Tandem PCIe Design Flow

On the AMD website, search for the KCU116 PCIe Tutorial and download the latest version for the example design.

Click on "XTP642 -- KCU116 PCIe Tutorial (v8.0)" to view the PDF slides for creating an example PCIe design. Click on "rdf0412-kcu116-pcie-c-2019-1.zip" to download the design files.

Extract the contents of "ready_for_download" from the downloaded design file to the C:\ drive or your preferred directory.

Configure the following settings in the "Basic " tab. Leave the default "Component Name".

Change the "Mode" to Advanced to unlock all of the features of the IP. Make sure the "Device/Port Type" is PCI Express Endpoint device and the "PCIe Block Location" is at X0Y0 . Change the "Lane Width" to X1 or depending on user specification and the "Maximum Link Speed" to 8.0 GT/s (Gen3). Check the "Reference Clock Frequency (MHz)" is set to 100MHz . Select Tandem PCIe from "Tandem Configuration or Partial Reconfiguration".

相关推荐
FakeOccupational2 小时前
【电路笔记 通信】AXI4-Lite协议 FPGA实现 & Valid-Ready Handshake 握手协议
笔记·fpga开发
I'm a winner2 小时前
FPGA+护理:跨学科发展的探索(五)
fpga开发
Turing_kun19 小时前
基于FPGA的实时图像处理系统(1)——SDRAM回环测试
fpga开发
I'm a winner2 天前
新手入门Makefile:FPGA项目实战教程(二)
笔记·fpga开发
我爱C编程2 天前
基于FPGA的8PSK+卷积编码Viterbi译码通信系统,包含帧同步,信道,误码统计,可设置SNR
fpga开发·通信·8psk·帧同步·snr·卷积编码·维特比译码
I'm a winner2 天前
新手入门 Makefile:FPGA 项目实战教程(三)
fpga开发
范纹杉想快点毕业2 天前
嵌入式 C 语言编程规范个人学习笔记,参考华为《C 语言编程规范》
linux·服务器·数据库·笔记·单片机·嵌入式硬件·fpga开发
lazyduck3 天前
从半年到一年的 bug 往事:TCP modbus的卡死与补救
fpga开发·modbus
范纹杉想快点毕业3 天前
《嵌入式 C 语言编码规范与工程实践个人笔记》参考华为C语言规范标准
服务器·c语言·stm32·单片机·华为·fpga开发·51单片机
Chipi Chipi3 天前
FPGA即插即用Verilog驱动系列——串口数据、命令解析
fpga开发