module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
reg q1,q2,q3;
always@(posedge clk)begin
if(~resetn)begin
q1 <=0;
q2 <=0;
q3 <=0;
out<=0;
end
else
begin
q1 <= in;
q2 <= q1;
q3 <= q2;
out<=q3;
end
end
endmodule
以上代码是根据逻辑写的,细看好像是循环左移位。移3位
module top_module (
input logic clk,
input logic resetn, // synchronous reset
input logic in,
output logic out);
var logic [3:0] Q ;
always@(posedge clk) begin
if(!resetn)
Q <= 0 ;
else
Q <= {in,Q[3:1]} ;
end
assign out = Q[0] ;
endmodule