（1）实验目标：在PC机上使用串口助手将一幅像素点为480*480的图片以分辨率800*480@60 的形式发给FPGA，FPGA以外接DDR3 SDRAM 做缓存，将接收到的图片通过TFT显示屏（显色模式：RGB565）显示出来。
（2）硬件设备：
- TFT显示屏（采用800*600@60Hz的触摸tft显示屏）
（3）程序参考66实验，此处仅提供顶层程序：
module rs232_ddr_tft
(
input wire clk ,
input wire reset_n ,
input wire rx ,
//vga-hdmi接口
output wire tft_hsync ,
output wire tft_vsync ,
output wire tft_clk ,
output wire tft_bl ,
output wire [15:0] tft_rgb ,
output wire tft_DE ,
//DDR3物理接口
output wire [14:0] ddr3_addr ,
output wire [2:0] ddr3_ba ,
output wire ddr3_cas_n ,
output wire ddr3_ck_n ,
output wire ddr3_ck_p ,
output wire ddr3_cke ,
output wire ddr3_ras_n ,
output wire ddr3_reset_n ,
output wire ddr3_we_n ,
inout wire [31:0] ddr3_dq ,
inout wire [3:0] ddr3_dqs_n ,
inout wire [3:0] ddr3_dqs_p ,
output wire ddr3_cs_n ,
output wire [3:0] ddr3_dm ,
output wire ddr3_odt
);
wire clk_33M ;
wire clk_320M ;
wire locked ;
wire rst_n ;
wire ui_clk ;
wire ui_rst ;
wire data_rden ;
wire [15:0] data_rd ;
wire init_rst_n ;
wire init_calib_complete ;
wire [7:0] rx_data ;
wire rx_done ;
wire [15:0] data_in ;
wire [9:0] hang ;
wire [9:0] lie ;
wire img_valid ;
reg [20:0] done_cnt ;
reg [15:0] temp_wrdata ;
reg data_wren ;
parameter IMG_LENGTH = 480;
parameter IMG_WIDE = 480;
pll pll_inst
(
.clk_33M (clk_33M ),
.clk_320M (clk_320M ),
.reset (~reset_n ),
.locked (locked ),
.clk_in1 (clk )
);
assign tft_clk = clk_33M;
always@(posedge clk or negedge init_rst_n)
if(!init_rst_n)
done_cnt <= 21'd0;
else if(rx_done)
done_cnt <= done_cnt + 21'd1;
else
done_cnt <= done_cnt;
always@(posedge clk or negedge init_rst_n)
if(!init_rst_n)
temp_wrdata <= 16'd0;
else if(rx_done)
temp_wrdata <= {temp_wrdata[7:0],rx_data};
else
temp_wrdata <= temp_wrdata;
always@(posedge clk or negedge init_rst_n)
if(!init_rst_n)
data_wren <= 1'd0;
else if(rx_done && done_cnt[0])
data_wren <= 1'd1;
else
data_wren <= 1'd0;
assign rst_n = reset_n & locked ;
axi_ddr3_top axi_ddr3_top_inst
(
.ddr3_clk (clk_320M ),
.reset_n (rst_n ),
.pingpang (1'd0 ),
.ui_clk (ui_clk ),
.ui_rst (ui_rst ),
.wr_b_addr (32'd0 ),
.wr_e_addr (IMG_LENGTH*IMG_WIDE*2 ),
.wr_clk (clk ),
.data_wren (data_wren ),
.data_wr (temp_wrdata ),
.wr_rst (1'd0 ),
.rd_b_addr (32'd0 ),
.rd_e_addr (IMG_LENGTH*IMG_WIDE*2 ),
.rd_clk (clk_33M ),
.data_rden (data_rden ),
.data_rd (data_rd ),
.rd_rst (1'd0 ),
.read_enable (1'd1 ),
.rd_data_valid (),
.ddr3_addr (ddr3_addr ),
.ddr3_ba (ddr3_ba ),
.ddr3_cas_n (ddr3_cas_n ),
.ddr3_ck_n (ddr3_ck_n ),
.ddr3_ck_p (ddr3_ck_p ),
.ddr3_cke (ddr3_cke ),
.ddr3_ras_n (ddr3_ras_n ),
.ddr3_reset_n (ddr3_reset_n ),
.ddr3_we_n (ddr3_we_n ),
.ddr3_dq (ddr3_dq ),
.ddr3_dqs_n (ddr3_dqs_n ),
.ddr3_dqs_p (ddr3_dqs_p ),
.init_calib_complete (init_calib_complete ),
.ddr3_cs_n (ddr3_cs_n ),
.ddr3_dm (ddr3_dm ),
.ddr3_odt (ddr3_odt )
);
assign init_rst_n = reset_n & init_calib_complete ;
rs232_rx rs232_rx_inst
(
.clk (clk ),
.reset_n (init_rst_n),
.rx (rx ),
.rx_start (1'd1 ),
.rx_data (rx_data ),
.rx_done (rx_done )
);
tft_ctrl tft_ctrl_inst
(
.tft_clk (clk_33M ),
.reset_n (init_rst_n ),
.data_in (data_in ),
.hang (hang ),
.lie (lie ),
.hsync (tft_hsync ),
.vsync (tft_vsync ),
.rgb_tft (tft_rgb ),
.tft_DE (tft_DE )
);
assign data_in = (img_valid) ? data_rd : 16'hffff;
assign img_valid = (hang >= 160) && (hang < 640) && (lie >= 1);
assign data_rden = img_valid;
assign tft_bl = 1'd1;
endmodule（3）XDC文件：
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports reset_n]
set_property IOSTANDARD LVCMOS33 [get_ports rx]
set_property IOSTANDARD LVCMOS33 [get_ports tft_bl]
set_property IOSTANDARD LVCMOS33 [get_ports tft_clk]
set_property IOSTANDARD LVCMOS33 [get_ports tft_DE]
set_property IOSTANDARD LVCMOS33 [get_ports tft_hsync]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tft_rgb[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports tft_vsync]
set_property PACKAGE_PIN W19 [get_ports clk]
set_property PACKAGE_PIN N15 [get_ports reset_n]
set_property PACKAGE_PIN P17 [get_ports rx]
set_property PACKAGE_PIN W10 [get_ports tft_bl]
set_property PACKAGE_PIN T14 [get_ports tft_DE]
set_property PACKAGE_PIN Y13 [get_ports tft_hsync]
set_property PACKAGE_PIN AA11 [get_ports tft_clk]
set_property PACKAGE_PIN W12 [get_ports tft_vsync]
set_property PACKAGE_PIN W16 [get_ports {tft_rgb[15]}]
set_property PACKAGE_PIN W14 [get_ports {tft_rgb[14]}]
set_property PACKAGE_PIN U16 [get_ports {tft_rgb[13]}]
set_property PACKAGE_PIN W15 [get_ports {tft_rgb[12]}]
set_property PACKAGE_PIN T16 [get_ports {tft_rgb[11]}]
set_property PACKAGE_PIN AB13 [get_ports {tft_rgb[10]}]
set_property PACKAGE_PIN AA10 [get_ports {tft_rgb[9]}]
set_property PACKAGE_PIN Y14 [get_ports {tft_rgb[8]}]
set_property PACKAGE_PIN Y11 [get_ports {tft_rgb[7]}]
set_property PACKAGE_PIN V13 [get_ports {tft_rgb[6]}]
set_property PACKAGE_PIN AA13 [get_ports {tft_rgb[5]}]
set_property PACKAGE_PIN AB11 [get_ports {tft_rgb[4]}]
set_property PACKAGE_PIN Y12 [get_ports {tft_rgb[3]}]
set_property PACKAGE_PIN V10 [get_ports {tft_rgb[2]}]
set_property PACKAGE_PIN V14 [get_ports {tft_rgb[1]}]
set_property PACKAGE_PIN W11 [get_ports {tft_rgb[0]}]（4）引脚分配（XDC文件可以体现部分）以及实验现象
