1、Vscode下载安装
详见另一篇文章：
https://blog.csdn.net/weixin_61081689/article/details/143469236?spm=1001.2014.3001.55012、Verilog-HDL插件
自定义代码补全：
在Vscode+Anaconda配置Python环境_vscode配置python及anaconda-CSDN博客已经指出插件的位置，只需要找到extensions\mshr-h.veriloghdl-1.15.5\snippets\verilog.json文件修改即可
修改的内容如下：
{
"head": {
"prefix": "head",
"body": [
"// +FHDR----------------------------------------------------------------------------",
"// Project Name : ${1:FPGA/IC_Design}",
"// Device : ${2:Xilinx/Synopsys}",
"// Author : ${3:yourname}",
"// File Name : ${TM_FILENAME}",
"// Data : $CURRENT_YEAR/$CURRENT_MONTH/$CURRENT_DATE $CURRENT_HOUR:$CURRENT_MINUTE:$CURRENT_SECOND",
"// Description : ",
" /*",
" Functions implemented",
" */",
"// -FHDR----------------------------------------------------------------------------"
],
"description": "Insert a module with head"
},
"module with parameters": {
"prefix": "module #",
"body": [
"`timescale 1ps/1ps",
"module ${1:moduleName} #(",
"\tparameters\t${2:NAMEWIDTH} = $3\t//",
") (",
"// Input",
"\tinput\t[${4:WIDTH} - 1 : 0]\t${5:inputname}\t//",
"// Output",
"\toutput reg [${6:WIDTH} - 1 : 0]\t${7:outputname}\t//",
");",
"\t$0",
"endmodule"
],
"description": "Insert a module with parameter"
},
"module without parameters": {
"prefix": "module",
"body": [
"`timescale 1ps/1ps",
"module ${1:moduleName} (",
"// Input",
"\tinput\t[${2:WIDTH} - 1 : 0]\t${3:inputname}\t//",
"// Output",
"\toutput reg [${4:WIDTH} - 1 : 0]\t${5:outputname}\t//",
");",
"\t$0",
"endmodule"
],
"description": "Insert a module without parameter"
},
"instantiate module": {
"prefix": ["set module", "instantiate module"],
"body": [
"${1:mod_name} ${2:instance_name} (${3:.*}$0);"
],
"description": "set module, mod i0 (.*);"
},
"always combinatorial logic": {
"prefix": "always comb",
"body": [
"always @(*) begin",
"\t$1",
"end"
],
"description": "always@(*)"
},
"always sequential logic p": {
"prefix": "always p",
"body": [
"always @(posedge ${1:clk}) begin",
"\t$2",
"end"
],
"description": "always @(posedge clk)"
},
"always sequential logic n": {
"prefix": "always n",
"body": [
"always @(negedge ${1:clk}) begin",
"\t$2",
"end"
],
"description": "always @(negedge clk)"
},
"always sequential logic pn": {
"prefix": "always pn",
"body": [
"always @(posedge ${1:clk} or negedge ${2:rst_n}) begin",
"\t$3",
"end"
],
"description": "always @(posedge clk or negedge rst_n)"
},
"always sequential logic pp": {
"prefix": "always pp",
"body": [
"always @(posedge ${1:clk} or posedge ${2:rst}) begin",
"\t$3",
"end"
],
"description": "always @(posedge clk or posedge rst)"
},
"always sequential logic nn": {
"prefix": "always nn",
"body": [
"always @(negedge ${1:clk} or negedge ${2:rst_n}) begin",
"\t$3",
"end"
],
"description": "always @(negedge clk or negedge rst_n)"
},
"begin/end": {
"prefix": "begin",
"body": [
"begin",
"\t$1",
"end"
],
"description": "Insert a begin ... end block"
},
"end": {
"prefix": "end",
"body": "end",
"description": "Insert end keyword"
},
"initial": {
"prefix": "initial",
"body": [
"initial begin",
"\t$0",
"end"
],
"description": "initial begin ... end"
},
"case": {
"prefix": "case",
"body": [
"case (${1:param})",
"\t$2: $3",
"\tdefault: $4",
"endcase"
],
"description": "case () ... endcase"
},
"casex": {
"prefix": "casex",
"body": [
"casex (${1:param})",
"\t$2: $3",
"\tdefault: $4",
"endcase"
],
"description": "casex () ... endcase"
},
"casez": {
"prefix": "casez",
"body": [
"casez (${1:param})",
"\t$2: $3",
"\tdefault: $4",
"endcase"
],
"description": "casez () ... endcase"
},
"reg": {
"prefix": "reg",
"body": [
"reg $1; //"
],
"description": "reg reg_name;"
},
"regarray": {
"prefix": ["regarray", "reg ["],
"body": [
"reg [$1:$2] $3; //"
],
"description": "reg [N:0] reg_name;"
},
"regmemory": {
"prefix": ["regmemory","memory"],
"body": [
"reg [$1:$2] $3 [$4:$5]; //"
],
"description": "reg [N:0] reg_name [0:M];"
},
"input": {
"prefix": "input",
"body": [
"input\t${1:inputname}; //"
],
"description": "input input_name;"
},
"inputarray": {
"prefix": "input [",
"body": [
"input\t[$1:$2]\t${3:inputname}; //"
],
"description": "input [N:0] input_name;"
},
"output": {
"prefix": "output",
"body": [
"output reg ${1:outputname}; //"
],
"description": "output reg output_name;"
},
"outputarray": {
"prefix": "output [",
"body": [
"output reg [$1:$2]\t${3:outputname}; //"
],
"description": "output reg [N:0] output_name;"
},
"wire": {
"prefix": "wire",
"body": [
"wire $1; //"
],
"description": "wire wire_name;"
},
"wirearray": {
"prefix": ["wirearray", "wire ["],
"body": [
"wire [$1:$2] $3; //"
],
"description": "wire [N:0] wire_name;"
},
"array": {
"prefix": "array",
"body": "[${1:8}:${2:0}]$0 //",
"description": "insert [x:y]"
},
"parameter": {
"prefix": "parameter",
"body": [
"parameters\t${1:NAMEWIDTH} = $2\t//"
],
"description": "paramter var = val;"
},
"localparam": {
"prefix": "localparam",
"body": "localparam\t${1:NAMEWIDTH} = $2;\t//",
"description": "localparam var = val"
},
"integer": {
"prefix": "integer",
"body": "integer $1; //",
"description": "integer int_name"
},
"signed": {
"prefix": "signed",
"body": "signed $1 $2; //",
"description": "signed datatype name"
},
"include": {
"prefix": ["include", "`include"],
"body": [
"`include \"$1\""
],
"description": "`include \"..\""
},
"define": {
"prefix": ["def", "define", "`define"],
"body": [
"`define ${1:macro}"
],
"description": "`define macro"
},
"ifdef": {
"prefix": ["ifdef", "`ifdef"],
"body": "`ifdef ${1:macro}",
"description": "`ifdef macro"
},
"ifndef": {
"prefix": ["ifndef", "`ifndef"],
"body": "`ifndef ${1:macro}",
"description": "`ifndef macro"
},
"elsif": {
"prefix": ["elsif", "`elsif"],
"body": "`elsif ${1:macro}",
"description": "`elsif macro"
},
"endif": {
"prefix": ["endif", "`endif"],
"body": "`endif ${1:macro}",
"description": "`endif macro"
},
"undef": {
"prefix": ["undef", "`undef"],
"body": "`undef ${1:macro}",
"description": "`undef macro"
},
"timescale": {
"prefix": ["ts", "timescale", "`timescale"],
"body": [
"`timescale ${1:1ps}/${2:1ps}$0"
]
},
"default_nettype": {
"prefix": ["default_nettype", "`default_nettype"],
"body": "`default_nettype ${1:none}",
"description": "Set default nettype"
},
"ternary": {
"prefix": "ternary",
"body": [
"$1 ? $2 : $3"
],
"description": "a ? b : c"
},
"if": {
"prefix": "if",
"body": [
"if (${1:conditions}) begin",
"\t$0",
"end"
],
"description": "if (...) begin ... end"
},
"ifelse": {
"prefix": "ifelse",
"body": [
"if (${1:conditions}) begin",
"\t$2",
"end else begin",
"\t$3",
"end"
],
"description": "if (...) begin ... end else begin ... end"
},
"for loop": {
"prefix": "for",
"body": [
"for ($1 = $2; $3; $4) begin",
"\t$0",
"end"
],
"description": "for (...) begin ... end"
},
"while loop": {
"prefix": "while",
"body": [
"while ($1) begin",
"\t$2",
"end"
],
"description": "while (...) begin ... end"
},
"forever": {
"prefix": "forever",
"body": [
"forever begin",
"\t$0",
"end"
],
"description": "forever begin ... end"
},
"function": {
"prefix": "function",
"body": [
"function $1;",
"\t$2;",
"\t$3",
"endfunction"
],
"description": "function (...) ... endfunction"
},
"generate": {
"prefix": "generate",
"body": [
"generate",
"\t$1",
"endgenerate"
],
"description": "generate (...) ... endgenerate"
},
"genvar": {
"prefix": "genvar",
"body": "genvar $1",
"description": "genvar i"
},
"testbench template": {
"prefix": ["tb", "testbench"],
"body": [
"`include \"$1.v\"",
"`default_nettype none",
"",
"module tb_$1;",
"reg clk;",
"reg rst_n;",
"",
"$1 $3",
"(",
"\t.rst_n (rst_n),",
"\t.clk (clk),",
");",
"",
"localparam CLK_PERIOD = 10;",
"always #(CLK_PERIOD/2) clk=~clk;",
"",
"initial begin",
"\t\\$dumpfile(\"tb_$1.vcd\");",
"\t\\$dumpvars(0, tb_$1);",
"end",
"",
"initial begin",
"\t#1 rst_n<=1'bx;clk<=1'bx;",
"\t#(CLK_PERIOD*3) rst_n<=1;",
"\t#(CLK_PERIOD*3) rst_n<=0;clk<=0;",
"\trepeat(5) @(posedge clk);",
"\trst_n<=1;",
"\t@(posedge clk);",
"\trepeat(2) @(posedge clk);",
"\t\\$finish(2);",
"end",
"",
"endmodule",
"`default_nettype wire"
],
"description": "testbench template"
}
}(1)自动生成文件头示范，按Tab键进行跳转修改的位置，输入head
(2)module块生成，两种格式，一种是带参数module #，一个是不带参数module
(3)几种always块，always comb,always p,always n,always pp,always pn,always nn
(4)verilog 输入、输出、数据类型和参数定义：input，input [，output，output [，wire，wire [，reg，reg [，memory，parameters，localparam；
(6)if...else和case：if，ifelse，case
3、优化verilog高亮插件Verilog highlight
4、静态语法检查与定义跳转
（1）安装ctags软件
下载地址：
通过百度网盘分享的文件：ctags-2023-02-15_p6.0.20230212.0-2-...
链接：https://pan.baidu.com/s/1ym8oFM3940Hhw_5kyVyTLg
提取码：qsmo
解压压缩包放在E:\vscode\extensions\ctags路径中，最好是全英文路径
把ctag.exe添加到环境变量中，系统和用户都添加上。
查看安装是否成功：在终端输入ctags --version打印以下信息
（2）安装iverilog软件
下载地址：
通过百度网盘分享的文件：iverilog-v11-20210204-x64_setup.exe
链接：https://pan.baidu.com/s/1FgCETVCrdGsQVIlTCq5tsA
提取码：wi0j
安装选择：
查看安装是否成功：在终端输入iverilog打印以下信息
（3）语法检查插件配置
ctags的路径指定：E:\vscode\extensions\ctag\ctags.exe
linter配置：
最终效果：使用中文分号，在保存后立马检测出来
（4）定义跳转
效果：
5、自动例化tb模板
需要安装verilog_test插件
需要安装好python，参考之前的文章：Vscode+Anaconda配置Python环境_vscode配置python及anaconda-CSDN博客
之后在终端通过pip安装chardet库：pip install chardet
在VScode中键盘输入ctrl+shift+p 打开命令，输入testbench，自动生成tb，直接粘贴即可。
模块例化在VScode中键盘输入ctrl+shift+p 打开命令，输入Instance即可。
6、功能仿真以及使用GKTwave或者自带插件查看波形
使用Vscode的终端进行编译，首先需要在，tb文件里面加入以下内容：
initial begin
$dumpfile("./sim/wave.vcd"); // 指定VCD文件的名字为wave.vcd，仿真信息将记录到此文件
$dumpvars(0, tb); // 指定层次数为0，则tb模块及其下面各层次的所有信号将被记录
#10000 $finish;
end需要运行以下脚本，根据自己的路径进行修改，前提需要安装python，参考之前的文章：Vscode+Anaconda配置Python环境_vscode配置python及anaconda-CSDN博客
python
import os
import shutil
import subprocess
# 遍历当前路径下所有.v文件
def findv(paths = os.walk(r'.'), rule = ".v"):
listv = []
for path, dir_lst, file_lst in paths:
for file_name in file_lst:
if file_name.endswith(rule):
listv.append(str(os.path.join(path, file_name)))
return listv
# 先清空原本编译缓存文件，再创建
shutil.rmtree("./sim")
os.makedirs("./sim")
# iverilog程序
iverilog_cmd = ['iverilog']
# 编译生成文件
iverilog_cmd += ['-o', r'./sim/out.vvp']
# 头文件(defines.v)路径pwd
# iverilog_cmd += ['-I', r'.']
# 宏定义，仿真输出文件
# iverilog_cmd += ['-D', r'OUTPUT="./sim/signature.output"']
# 添加.v文件
for v in findv():
iverilog_cmd.append(v)
# 1.编译文件
print(iverilog_cmd)
process_complice = subprocess.Popen(iverilog_cmd)
try:
process_complice.wait(timeout=10)
except subprocess.TimeoutExpired:
print('!!!Fail, process_complice timeout!!!')
# 2.运行
vvp_cmd = [r'vvp']
vvp_cmd.append(r'./sim/out.vvp')
process = subprocess.Popen(vvp_cmd)
try:
process.wait(timeout=10)
except subprocess.TimeoutExpired:
print('!!!Fail, vvp exec timeout!!!')
print("Simulation completed!!")在终端输入：python .\simulation.py，自动编译生成.vcd文件
（1）可以使用GTKwave打开波形文件，只需要在终端输入：gtkwave .\sim\wave.vcd
（2）使用vscode里面的插件
双击打开.vcd文件就可以查看了
