EE213 Lab2 hspice simulation R/C-V Characteristics

[0 前言](#0 前言)

[1 仿真目标](#1 仿真目标)

[2 Resistance of a transistor](#2 Resistance of a transistor)

[2.1 NMOS](#2.1 NMOS)

[2.2 PMOS](#2.2 PMOS)

[3 Gate capacitance versus gate voltage](#3 Gate capacitance versus gate voltage)

[3.1 NMOS(Cg-Vgs)](#3.1 NMOS(Cg-Vgs))

0 前言

记录一下来到skd上的强度比较大的一门课，数字集成电路2的lab设计还是蛮好的，该帖非详细教程只是单纯的写一些思虑并用作笔记，新手小白欢迎交流，有错勿喷！

1 仿真目标

主要仿真45nm MOS管的R/C-V特性

2 Resistance of a transistor

Circuit diagrams used

2.1 NMOS

2.1.1 simulation code

bash 复制代码

* 45nm NMOS Simulation  
.options brief post=2 probe

.temp 25
.INCLUDE 'NMOS_VTL.inc'
.param Vdd=0.4v

Vgs nG 0 DC Vdd
Vds nD 0 DC 1V

M0 nD nG 0 0 NMOS_VTL W=90n L=50n M=1
c1 nD 0 1p

.dc Vds 0 1.8 0.01  Vdd 0.4 1.8 0.2

.param Vgs_half_val='Vdd/2'

.meas I_half FIND I(M0) WHEN V(nD)=Vgs_half_val

.meas I_full FIND I(M0) WHEN V(nD)=Vdd

.meas R_half PARAM='Vgs_half_val / I_half'
.meas R_full PARAM='Vdd / I_full'
.meas R_eq PARAM='(R_half+R_full)/2'

.probe I(M0)
.print I(M0)

.end

2.1.2 simulation wave

2.1.3 Req-Vdd

提取数据，使用matlab计算绘图

Matlab 复制代码

% 定义 Vdd 范围
Vdd = [0.4 0.6 0.8 1 1.2 1.4 1.6 1.8];

Req = [22.2786 10.2313 7.8929 6.9778 6.5133 6.2463 6.0804 5.9693];

% 绘图
figure;
plot(Vdd, Req, 'LineWidth', 2);
xlabel('V_{dd} (V)');
ylabel('R_{eq} (kΩ)');
title('45nm NMOS R_{eq} vs V_{dd}');
grid on;

2.2 PMOS

2.2.1 simulation code

bash 复制代码

* 45nm PMOS Simulation  
.options brief post=2 probe

.temp 25
.INCLUDE 'PMOS_VTL.inc'
.param Vdd=-0.4v

Vgs nG 0 DC Vdd
Vds nD 0 DC 1V

M0 nD nG 0 0 PMOS_VTL W=90n L=150n M=1
c1 nD 0 1p

.dc Vds 0 -1.8 0.01  Vdd -0.4 -1.8 0.2

.param Vgs_half_val='Vdd/2'

.meas I_half FIND I(M0) WHEN V(nD)=Vgs_half_val

.meas I_full FIND I(M0) WHEN V(nD)=Vdd

.meas R_half PARAM='Vgs_half_val / I_half'
.meas R_full PARAM='Vdd / I_full'
.meas R_eq PARAM='(R_half+R_full)/2'

.probe I(M0)
.print I(M0)

.end

2.2.2 simulation wave

2.2.3 Req-Vdd

提取数据，使用matlab计算绘图

Matlab 复制代码

% 定义 Vdd 范围
Vdd = [-0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8];

Req = [229.7298 73.6631 46.7788 36.648 31.4865 28.4305 26.5153 25.335];

% 绘图
figure;
plot(Vdd, Req, 'LineWidth', 2);
xlabel('V_{dd} (V)');
ylabel('R_{eq} (kΩ)');
title('45nm PMOS R_{eq} vs V_{dd}');
grid on;

3 Gate capacitance versus gate voltage

3.1 NMOS(Cg-Vgs)

3.1.1 simulation code

bash 复制代码

.title Cg-VGS For45nm NMOS
Vgn gn 0 dc 1.1v ac '0.5/3.1415926'
Vdn dn 0 dc 1.1v


MN O gn 0 0 NMOS_VTL L=50e-9 W=90e-9

.temp 25
.op
.dc sweep Vgn -1.1 1.1 0.01

.option dccap brief accurate nomod post = 2
.inc 'NMOS_VTL.inc'

.probe CGD=par('-lx19(MN)')CGS=par('-lx20(MN)') CGB=par('lx18(MN)+lx19(MN)+lx20(MN)')
 +CG=par('CGD+CGS+CGB')

.end

EE213 Lab2 hspice simulation R/C-V Characteristics

0 前言

1 仿真目标

2 Resistance of a transistor

2.1 NMOS

2.1.1 simulation code

2.1.2 simulation wave

2.1.3 Req-Vdd

2.2 PMOS

2.2.1 simulation code

2.2.2 simulation wave

2.2.3 Req-Vdd

3 Gate capacitance versus gate voltage

3.1 NMOS(Cg-Vgs)

3.1.1 simulation code

3.1.2 simulation wave