FPGA设计中IOB约束

IOB，是Input Output Buffer的缩写，

Vivado工具对IOB约束的英文解释为：Place Register into IOB，

IOB约束多用于高速数据采样中，用于减小输入信号引脚到寄存器的路径延时，同时也用于保证多次综合后的路径延时基本不变。

Verilog中IOB约束的例子：

（*IOB="true"*）reg adc_in_iob;

always @(posedge clk) begin
	if(rst)
		adc_in_iob <= 1'b0;
	else
		adc_in_iob <= adc_in;
end

VHDL中IOB约束的例子：

signal cmos_din_iob : std_logic_vector(3 downto 0);
attribute IOB : string;
attribute IOB of cmos_din_iob : signal is "TRUE";

process(clk,rst)
begin
	if rst ='1' then
		cmos_din_iob <= (others=>'0');
	elsif clk'event and clk='1' then
		cmos_din_iob <= cmos_din;
	end if;
end process;