GD32 CAN1和TIMER0同时开启问题

背景：今天在一个项目调试的时候发现了一些问题，由此贴记录一下问题解决的过程。

使用的芯片是GD32F305VE。使用到了CAN1和TIMER0。在使用这连个外设的时候发送了一些问题。

单独使用CAN1。功能正常。

单独使用TIMER0。配置为输出模式。功能正常。

但是当两个功能同时使用，初始化的时候，就出问题了。

1、引脚配置

cpp 复制代码

//TIMER0 引脚定义
#define   TIMER0_CH2_GPIO_PIN              GPIO_PIN_10
#define   TIMER0_CH1_GPIO_PIN              GPIO_PIN_9
#define   TIMER0_CH2N_GPIO_PIN             GPIO_PIN_15
#define   TIMER0_CH1N_GPIO_PIN             GPIO_PIN_14

cpp 复制代码

//CAN1引脚定义
#define   CAN1_CLOCK                    RCU_GPIOB
#define   CAN1_GPIO                     GPIOB
#define   CAN1_TX_GPIO_PIN              GPIO_PIN_13
#define   CAN1_RX_GPIO_PIN              GPIO_PIN_12

从引脚上看，每个是没有用到重复的引脚的。都是单独分开。

2、发现问题

但是这时候，会导致一个问题。

CAN1的初始化失败了。

cpp 复制代码

//这是底层的库函数，CAN初始化
ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init)
{
    uint32_t timeout = CAN_TIMEOUT;
    ErrStatus flag = ERROR;
    
    /* disable sleep mode */
    CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
    /* enable initialize mode */
    CAN_CTL(can_periph) |= CAN_CTL_IWMOD;
    /* wait ACK */
    while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
        timeout--;
    }
    /* check initialize working success */
    if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
        flag = ERROR;
    }else{
        /* set the bit timing register */
        CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \
                              BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \
                              BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \
                              BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \
                              BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U)));

        /* time trigger communication mode */
        if(ENABLE == can_parameter_init->time_triggered){
            CAN_CTL(can_periph) |= CAN_CTL_TTC;
        }else{
            CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
        }
        /* automatic bus-off managment */
        if(ENABLE == can_parameter_init->auto_bus_off_recovery){
            CAN_CTL(can_periph) |= CAN_CTL_ABOR;
        }else{
            CAN_CTL(can_periph) &= ~CAN_CTL_ABOR;
        }
        /* automatic wakeup mode */
        if(ENABLE == can_parameter_init->auto_wake_up){
            CAN_CTL(can_periph) |= CAN_CTL_AWU;
        }else{
            CAN_CTL(can_periph) &= ~CAN_CTL_AWU;
        }
        /* automatic retransmission mode disable */
        if(ENABLE == can_parameter_init->no_auto_retrans){
            CAN_CTL(can_periph) |= CAN_CTL_ARD;
        }else{
            CAN_CTL(can_periph) &= ~CAN_CTL_ARD;
        }
        /* receive fifo overwrite mode */        
        if(ENABLE == can_parameter_init->rec_fifo_overwrite){
            CAN_CTL(can_periph) |= CAN_CTL_RFOD;
        }else{
            CAN_CTL(can_periph) &= ~CAN_CTL_RFOD;
        } 
        /* transmit fifo order */
        if(ENABLE == can_parameter_init->trans_fifo_order){
            CAN_CTL(can_periph) |= CAN_CTL_TFO;
        }else{
            CAN_CTL(can_periph) &= ~CAN_CTL_TFO;
        }  
        /* disable initialize mode */
        CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD;
        timeout = CAN_TIMEOUT;
        /* wait the ACK */
        while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
            timeout--;
        }
        /* check exit initialize mode */
        if(0U != timeout){
            flag = SUCCESS;
        }
    }  
    return flag;
}