XCKU5P引脚约束

时钟

# 系统差分时钟引脚 (Positive)
set_property PACKAGE_PIN T24 [get_ports i_sys_clk_p]
set_property IOSTANDARD DIFF_SSTL12 [get_ports i_sys_clk_p]
set_property PACKAGE_PIN U24 [get_ports i_sys_clk_n]
set_property IOSTANDARD DIFF_SSTL12 [get_ports i_sys_clk_n]
create_clock -name sys_clk -period 5.000 [get_ports i_sys_clk_p]

串口

# UART 串口引脚
set_property PACKAGE_PIN AD13 [get_ports i_uart_rx]
set_property PACKAGE_PIN AC14 [get_ports o_uart_tx]
set_property IOSTANDARD LVCMOS33 [get_ports i_uart_rx]
set_property IOSTANDARD LVCMOS33 [get_ports o_uart_tx]  

LED

# LED 引脚（4个）
set_property PACKAGE_PIN H9  [get_ports {o_led[0]}]
set_property PACKAGE_PIN J9  [get_ports {o_led[1]}]
set_property PACKAGE_PIN G11 [get_ports {o_led[2]}]
set_property PACKAGE_PIN H11 [get_ports {o_led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_led[0] o_led[1] o_led[2] o_led[3]}]

数码管

# =============================================================================
# 7-Segment Display A (数码管 A 组)
# seg_a_n[0:7] 对应: A, B, C, D, E, F, G, DP (低电平有效)
# dig_a_n[0:3] 对应: DIG1, DIG2, DIG3, DIG4 (低电平有效)
# =============================================================================

# 段码 (Segments)
set_property PACKAGE_PIN C14 [get_ports {seg_a_n[0]}] ;# A
set_property PACKAGE_PIN C13 [get_ports {seg_a_n[1]}] ;# B
set_property PACKAGE_PIN B14 [get_ports {seg_a_n[2]}] ;# C
set_property PACKAGE_PIN A14 [get_ports {seg_a_n[3]}] ;# D
set_property PACKAGE_PIN A13 [get_ports {seg_a_n[4]}] ;# E
set_property PACKAGE_PIN A12 [get_ports {seg_a_n[5]}] ;# F
set_property PACKAGE_PIN B10 [get_ports {seg_a_n[6]}] ;# G
set_property PACKAGE_PIN A10 [get_ports {seg_a_n[7]}] ;# DP

# 位选 (Digit Select)
set_property PACKAGE_PIN D14 [get_ports {dig_a_n[0]}] ;# DIG1
set_property PACKAGE_PIN D13 [get_ports {dig_a_n[1]}] ;# DIG2
set_property PACKAGE_PIN C12 [get_ports {dig_a_n[2]}] ;# DIG3
set_property PACKAGE_PIN B12 [get_ports {dig_a_n[3]}] ;# DIG4

# =============================================================================
# 7-Segment Display B (数码管 B 组)
# seg_b_n[0:7] 对应: A, B, C, D, E, F, G, DP (低电平有效)
# dig_b_n[0:3] 对应: DIG1, DIG2, DIG3, DIG4 (低电平有效)
# =============================================================================

# 段码 (Segments)
set_property PACKAGE_PIN H14 [get_ports {seg_b_n[0]}] ;# A
set_property PACKAGE_PIN G14 [get_ports {seg_b_n[1]}] ;# B
set_property PACKAGE_PIN G12 [get_ports {seg_b_n[2]}] ;# C
set_property PACKAGE_PIN F12 [get_ports {seg_b_n[3]}] ;# D
set_property PACKAGE_PIN F14 [get_ports {seg_b_n[4]}] ;# E
set_property PACKAGE_PIN F13 [get_ports {seg_b_n[5]}] ;# F
set_property PACKAGE_PIN E13 [get_ports {seg_b_n[6]}] ;# G
set_property PACKAGE_PIN E12 [get_ports {seg_b_n[7]}] ;# DP

# 位选 (Digit Select)
set_property PACKAGE_PIN J13 [get_ports {dig_b_n[0]}] ;# DIG1
set_property PACKAGE_PIN H13 [get_ports {dig_b_n[1]}] ;# DIG2
set_property PACKAGE_PIN J15 [get_ports {dig_b_n[2]}] ;# DIG3
set_property PACKAGE_PIN J14 [get_ports {dig_b_n[3]}] ;# DIG4

# =============================================================================
# IO Standard (电平标准)
# =============================================================================
set_property IOSTANDARD LVCMOS33 [get_ports {seg_a_n[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dig_a_n[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_b_n[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dig_b_n[*]}]

拨码开关

# =============================================================================
# DIP Switches (拨码开关)
# sw_n[0:9] 对应板卡上的 SW1 到 SW10
# 逻辑说明：开关拨至 ON 时为低电平 (Active-Low)
# =============================================================================

set_property PACKAGE_PIN D10 [get_ports {sw_n[0]}] ;# SW1
set_property PACKAGE_PIN D11 [get_ports {sw_n[1]}] ;# SW2
set_property PACKAGE_PIN E10 [get_ports {sw_n[2]}] ;# SW3
set_property PACKAGE_PIN E11 [get_ports {sw_n[3]}] ;# SW4
set_property PACKAGE_PIN B11 [get_ports {sw_n[4]}] ;# SW5
set_property PACKAGE_PIN C11 [get_ports {sw_n[5]}] ;# SW6
set_property PACKAGE_PIN C9  [get_ports {sw_n[6]}] ;# SW7
set_property PACKAGE_PIN D9  [get_ports {sw_n[7]}] ;# SW8
set_property PACKAGE_PIN A9  [get_ports {sw_n[8]}] ;# SW9
set_property PACKAGE_PIN B9  [get_ports {sw_n[9]}] ;# SW10

# =============================================================================
# IO Standard (电平标准)
# =============================================================================
set_property IOSTANDARD LVCMOS33 [get_ports {sw_n[*]}]

压缩BIN及加快FPGA启动

# 压缩BIN及加快FPGA启动
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design]