Pass cfg from cmd to test

Pass cfg from cmd to test

  • [1 Pass cfg from sh to case](#1 Pass cfg from sh to case)
  • [1.1 v a l u e value valueplusargs()`](#1.1 v a l u e value valueplusargs()`)
  • [1.2 uvm_config_int::get()<--->uvm_set_config_int/string/](#1.2 uvm_config_int::get()<--->uvm_set_config_int/string/)

The article's purpose is to solve the flexity; you can pass cfg to test by cmd directly; this is convinent for you to control or constraint the case;
Now,there are two common ways to do it;

1 Pass cfg from sh to case

1.1 v a l u e value valueplusargs()`

In any compenent,you use the usage;

sv 复制代码
        function void base_test:build_phase();
                super.build_phase(phase);
                if(!$value$plusargs("mask_mode=%0d",mask_mode)) begin
                        `uvm_error("base_test","mask_mode is set to default");
                end
        endfunction:build_phase
sh 复制代码
        #在末尾添加参数run_opt;
        -run_opt  +mask_mode=9

1.2 uvm_config_int::get()<--->uvm_set_config_int/string/

In any component,you should code in it; Principle: It will creats a diction,then put it in pool; you will use get it at any time;

you can put the code anywhere;

sv 复制代码
        function void base_test:build_phase();
                super.build_phase(phase);
                if(!uvm_config_int::get(this,"","mask_mode",mask_mode)) begin
                        `uvm_error("base_test","mask_mode is set to default");
                end
        endfunction:build_phase 
sh 复制代码
#末尾添加参数
-run_opt  +uvm_set_config_int="uvm_test_top,mask_mode,12" &

Note the difference between the two ways;

Advantage: you can use it even under regression;

regression 复制代码
# Add in the regression.txt
TESTS += xx_test;+uvm_set_config_int="uvm_test_top,mask_mode,12"
相关推荐
apple_ttt6 天前
SystemVerilog学习——构造函数new
fpga开发·fpga·systemverilog·uvm
apple_ttt8 天前
SystemVerilog学习——虚拟接口(Virtual Interface)
fpga开发·fpga·systemverilog·uvm
小妖11601 个月前
uvm_info、uvm_warning,uvm_error、uvm_fatal
uvm·ic验证
逍遥xiaoy5 个月前
SystemVerilog测试框架示例
systemverilog·uvm
谷公子的藏经阁6 个月前
设计模式在芯片验证中的应用——迭代器
设计模式·systemverilog·uvm·芯片验证·design pattern
小邦是名小ICer1 年前
7.2 uvm_resource_db in UVM
uvm
一只迷茫的小狗1 年前
UVM建造测试用例
uvm
不动明王呀1 年前
uvm白皮书练习_ch2_ch231_加入transaction
uvm
mrbone111 年前
UVM-什么是UVM方法学
systemverilog·uvm·验证·方法学