This exercise is an extension of module_shift. Instead of module ports being only single pins, we now have modules with vectors as ports, to which you will attach wire vectors instead of plain wires. Like everywhere else in Verilog, the vector length of the port does not have to match the wire connecting to it, but this will cause zero-padding or trucation of the vector. This exercise does not use connections with mismatched vector lengths.
You are given a module my_dff8 with two inputs and one output (that implements a set of 8 D flip-flops). Instantiate three of them, then chain them together to make a 8-bit wide shift register of length 3. In addition, create a 4-to-1 multiplexer (not provided) that chooses what to output depending on sel[1:0]: The value at the input d, after the first, after the second, or after the third D flip-flop. (Essentially, sel selects how many cycles to delay the input, from zero to three clock cycles.)
The module provided to you is: module my_dff8 ( input clk, input [7:0] d, output [7:0] q );
The multiplexer is not provided. One possible way to write one is inside an always block with a case statement inside. (See also: mux9to1v)
译：
这个练习是module_shift模块的扩展。不同于模块端口只能是单个引脚，我们现在有的模块具有向量作为端口，你将连接向量而不是简单的线。 在Verilog的其他部分一样，端口的向量长度不必与连接到它的线匹配，但这会导致向量进行零填充或截断。这个练习不使用长度不匹配的连接。
你将得到一个名为my_dff8的模块，它有两个输入和一个输出（实现了一组8个D触发器）。实例化三个这样的模块，然后将它们串联起来，制作一个8位宽、长度为3的移位寄存器。此外，创建一个4选1多路选择器（未提供），根据sel[1:0]选择输出内容：输入d的值，在第一个、第二个或第三个D触发器之后的值。（本质上，sel选择输入延迟多少个时钟周期，从零到三个时钟周期。）
提供给你的模块是：module my_dff8 ( input clk, input [7:0] d, output [7:0] q );
多路选择器未提供。编写多路选择器的一种方法是在一个always块内使用case语句。（另见：mux9to1v）
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output [7:0] q
);
wire[7:0] q1,q2,q3;
my_dff8 d1(clk,d,q1);
my_dff8 d2(clk,q1,q2);
my_dff8 d3(clk,q2,q3);
always@(*)
case (sel)
2'h0: q = d ;
2'h1: q = q1;
2'h2: q = q2;
2'h3: q = q3;
endcase
endmodule
注释：
此题两个知识点
-
关于向量在模组中的应用，向量线的定义方法；
always@(*)
case (sel)
.......
endcase
的用法，类似于C语言的switch用法
运行结果;
