20240423给飞凌的OK3588-C开发板适配OV13855【绿屏】查找问题
2024/4/23 19:43
修改2个部分：
1、DTS中CAM1由ISP0处理修改为ISP1处理。【感觉修改为ISP1之后就不出错了，难道ISP0有问题？】
2、ov13855.c修改为 荣品的RK3588开发板提供的SDK Android12中获取的。【经过比对，感觉驱动改变不大！但是不做验证了】
瑞芯微RK3588开发板RK3588核心板rockchip 八核8K荣品RD-RK3588
RD-RK3588 链接：https://pan.baidu.com/s/1WAlkzARDpxV-2fd8gSPDiA 提取码：2*45
置顶发给新成员常见问题可以在Redmine 上在右上角搜索对应芯片型号查看
http://39.98.161.150:3088/issues/173
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【初始分析结论】
1、由于OV13855的硬件是4LANE的，初始怀疑是否因为只接受到2LANE的数据。【还有2LANE丢失了所以发绿】
在ov13855.c的每一个函数都加入打印，经过跟踪代码，发现ov13855.c默认写死为4lane，
并且给0x3016寄存器写入了0x72。
今后方便的时候，可以增加设备节点，在打开摄像头的时候，直接读取0x3016寄存器，确定是几LANE在工作！
或者在/sys/class中增加访问访问节点！
当然也可以通过示波器/逻辑分析仪测量MIPI信号【HS信号需要高端仪器，千元机逻辑分析仪即可测试LP信号】
2、更换为ISP1之后OV13855貌似就不闪退了。
3、绿色偏色的问题根据百度找到的CSDN的解释，说是驱动的问题。但是这个驱动在Orange pi5的Android12下可以正常点亮OV13855的，并以4K分辨率正常录像。当然接到飞凌OK3588-C和Orange pi5上的OV13855不是同一个！
https://blog.csdn.net/lj13329216157/article/details/132663037
RV1126 Linux IPC摄像机 索尼IMX415 摄像头调试
如果看到图像颜色不对、充满条纹等情况。像这样：
先别慌，至少有图像了不是。到这一步了至少说明通信时没问题了。应该检查摄像头参数或者驱动有没有设置对。由于驱动是系统自带的，出问题的可能性很小，我们先不管他。
详细的调试步骤：
1、看下在/etc/iqfiles目录下都有什么文件，另外，摄像头适配信息用需要下面的命令排查下，
root@ok3588:/etc/iqfiles#
root@ok3588:/etc/iqfiles# ls -l
total 15208
-rw-r--r-- 1 root root 294239 Mar 9 2023 gc02m2_LMM248_M2116A-223.json
-rw-r--r-- 1 root root 294091 Mar 9 2023 gc02m2_SLD-S10-M258-V1_TR215-H211.json
-rw-r--r-- 1 root root 294069 Mar 9 2023 gc02m2_THDS11073_YH-021B.json
-rw-r--r-- 1 root root 294128 Mar 9 2023 gc02m2_default_M216A.json
-rw-r--r-- 1 root root 293649 Mar 9 2023 gc2053_default_JX8006.json
-rw-r--r-- 1 root root 294204 Mar 9 2023 gc2093_SIDB205300385-VA_default.json
-rw-r--r-- 1 root root 294129 Mar 9 2023 gc2093_default_JX8006.json
-rw-r--r-- 1 root root 256457 Mar 9 2023 gc2385_HS5885-BNSM1018-V01_default.json
-rw-r--r-- 1 root root 292956 Mar 9 2023 gc4663_KS-ND-M1-V2_6040-A41-650IR.json
-rw-r--r-- 1 root root 293920 Mar 9 2023 gc5025_KYT-8647-V1_OPT532.json
-rw-r--r-- 1 root root 404181 Mar 9 2023 gc5035_XHG-RKX11F-V5_HR232H65.json
-rw-r--r-- 1 root root 294256 Mar 9 2023 gc5035_default_M512.json
-rw-r--r-- 1 root root 293492 Mar 9 2023 gc5035_default_PC5322-M5.json
-rw-r--r-- 1 root root 293941 Mar 9 2023 gc8034_RK-CMK-8M-2-v1_CK8401.json
-rw-r--r-- 1 root root 293996 Mar 9 2023 hi556_KYT-8607-V1.0_default.json
-rw-r--r-- 1 root root 293981 Mar 9 2023 hi846_KYT-8648-V1_YG589.json
-rw-r--r-- 1 root root 445263 Mar 9 2023 imx327_CMK-OT1607-FV1_M12-40IRC-4MP-F16.json
-rw-r--r-- 1 root root 689785 Mar 9 2023 imx415_CMK-OT2022-PX1_IR0147-50IRC-8M-F20.json
-rw-r--r-- 1 root root 804694 Mar 9 2023 imx464_CMK-OT1980-PX1_SHG102.json
-rw-r--r-- 1 root root 404659 Mar 9 2023 os04a10_CMK-OT1607-FV1_M12-40IRC-4MP-F16.json
-rw-r--r-- 1 root root 404194 Mar 9 2023 os04a10_CMK-OT1607-FV1_M12-60IRC-4MP-F16.json
-rw-r--r-- 1 root root 1544148 Mar 9 2023 os04a10_DH3588AVS6_default.json
-rw-r--r-- 1 root root 682975 Mar 9 2023 os04a10hk_CMK-OT1607-FV1_M12-40IRC-4MP-F16.json
-rw-r--r-- 1 root root 294181 Mar 9 2023 os08a10_RS-8MTP659-V1_default.json
-rw-r--r-- 1 root root 301041 Mar 9 2023 ov13850_ZC-OV13850R2A-V1_Largan-50064B31.json
-rw-r--r-- 1 root root 236952 Sep 15 2023 ov13850_forlinx_default.json
-rw-r--r-- 1 root root 338139 Mar 9 2023 ov13855_CMK-OT2016-FV1_default.json
-rw-r--r-- 1 root root 442537 Mar 9 2023 ov50c40_HZGA06_ZE0082C1.json
-rw-r--r-- 1 root root 404985 Mar 9 2023 ov5648_LMM248_YXC-M804A2.json
-rw-r--r-- 1 root root 404743 Mar 9 2023 ov5648_THDS11073_Largan-40122a1.json
-rw-r--r-- 1 root root 404649 Mar 9 2023 ov5670_LM50A60-V2_YXC-M804A2.json
-rw-r--r-- 1 root root 255381 Mar 9 2023 ov5695_TongJu_CHT842-MD.json
-rw-r--r-- 1 root root 404611 Mar 9 2023 ov8858_HS5885-BNSM1018-V01_default.json
-rw-r--r-- 1 root root 294070 Mar 9 2023 ov8858_HS8858-EB1008-V02_JX0843.json
-rw-r--r-- 1 root root 294049 Mar 9 2023 ov8858_SLD-S10-M258-V1_DL820B-D.json
-rw-r--r-- 1 root root 404292 Mar 9 2023 ov8858_XHG-RKX11B-V10_default.json
-rw-r--r-- 1 root root 404577 Mar 9 2023 s5k5e9_SHVK11-V3_HX-M0568E.json
-rw-r--r-- 1 root root 301122 Mar 9 2023 sc200ai_default_TP-8009A-IR.json
-rw-r--r-- 1 root root 293872 Mar 9 2023 sc200ai_default_TP-8009A-RGB.json
-rw-r--r-- 1 root root 294103 Mar 9 2023 sp250a_LM50A60-V2_M2116A-223.json
root@ok3588:/etc/iqfiles#
2、v4l2-ctl --list-devices
root@ok3588:/etc/iqfiles#
root@ok3588:/etc/iqfiles# v4l2-ctl --list-devices
rk_hdmirx (fdee0000.hdmirx-controller):
/dev/video17
rkisp-statistics (platform: rkisp):
/dev/video15
/dev/video16
rkcif-mipi-lvds (platform:rkcif):
/dev/media0
rkcif (platform:rkcif-mipi-lvds):
/dev/video0
/dev/video1
/dev/video2
/dev/video3
/dev/video4
/dev/video5
/dev/video6
/dev/video7
rkisp_mainpath (platform:rkisp1-vir0):
/dev/video8
/dev/video9
/dev/video10
/dev/video11
/dev/video12
/dev/video13
/dev/video14
/dev/media1
root@ok3588:/etc/iqfiles#
3、media-ctl -p -d /dev/media* 具体设备号需要看您适配的哪个
root@ok3588:/etc/iqfiles# media-ctl -p -d /dev/media*
Media controller API version 5.10.66
Media device information
driver rkcif
model rkcif-mipi-lvds
serial
bus info
hw revision 0x0
driver version 5.10.66
Device topology
- entity 1: stream_cif_mipi_id0 (1 pad, 8 links)
type Node subtype V4L flags 0
device node name /dev/video0
pad0: Sink
<- "rockchip-mipi-csi2":1 [ENABLED]
<- "rockchip-mipi-csi2":2 []
<- "rockchip-mipi-csi2":3 []
<- "rockchip-mipi-csi2":4 []
<- "rockchip-mipi-csi2":5 []
<- "rockchip-mipi-csi2":6 []
<- "rockchip-mipi-csi2":7 []
<- "rockchip-mipi-csi2":8 []
- entity 5: stream_cif_mipi_id1 (1 pad, 8 links)
type Node subtype V4L flags 0
device node name /dev/video1
pad0: Sink
<- "rockchip-mipi-csi2":1 []
<- "rockchip-mipi-csi2":2 [ENABLED]
<- "rockchip-mipi-csi2":3 []
<- "rockchip-mipi-csi2":4 []
<- "rockchip-mipi-csi2":5 []
<- "rockchip-mipi-csi2":6 []
<- "rockchip-mipi-csi2":7 []
<- "rockchip-mipi-csi2":8 []
- entity 9: stream_cif_mipi_id2 (1 pad, 8 links)
type Node subtype V4L flags 0
device node name /dev/video2
pad0: Sink
<- "rockchip-mipi-csi2":1 []
<- "rockchip-mipi-csi2":2 []
<- "rockchip-mipi-csi2":3 [ENABLED]
<- "rockchip-mipi-csi2":4 []
<- "rockchip-mipi-csi2":5 []
<- "rockchip-mipi-csi2":6 []
<- "rockchip-mipi-csi2":7 []
<- "rockchip-mipi-csi2":8 []
- entity 13: stream_cif_mipi_id3 (1 pad, 8 links)
type Node subtype V4L flags 0
device node name /dev/video3
pad0: Sink
<- "rockchip-mipi-csi2":1 []
<- "rockchip-mipi-csi2":2 []
<- "rockchip-mipi-csi2":3 []
<- "rockchip-mipi-csi2":4 [ENABLED]
<- "rockchip-mipi-csi2":5 []
<- "rockchip-mipi-csi2":6 []
<- "rockchip-mipi-csi2":7 []
<- "rockchip-mipi-csi2":8 []
- entity 17: rkcif_scale_ch0 (1 pad, 8 links)
type Node subtype V4L flags 0
device node name /dev/video4
pad0: Sink
<- "rockchip-mipi-csi2":1 []
<- "rockchip-mipi-csi2":2 []
<- "rockchip-mipi-csi2":3 []
<- "rockchip-mipi-csi2":4 []
<- "rockchip-mipi-csi2":5 [ENABLED]
<- "rockchip-mipi-csi2":6 []
<- "rockchip-mipi-csi2":7 []
<- "rockchip-mipi-csi2":8 []
- entity 21: rkcif_scale_ch1 (1 pad, 8 links)
type Node subtype V4L flags 0
device node name /dev/video5
pad0: Sink
<- "rockchip-mipi-csi2":1 []
<- "rockchip-mipi-csi2":2 []
<- "rockchip-mipi-csi2":3 []
<- "rockchip-mipi-csi2":4 []
<- "rockchip-mipi-csi2":5 []
<- "rockchip-mipi-csi2":6 [ENABLED]
<- "rockchip-mipi-csi2":7 []
<- "rockchip-mipi-csi2":8 []
- entity 25: rkcif_scale_ch2 (1 pad, 8 links)
type Node subtype V4L flags 0
device node name /dev/video6
pad0: Sink
<- "rockchip-mipi-csi2":1 []
<- "rockchip-mipi-csi2":2 []
<- "rockchip-mipi-csi2":3 []
<- "rockchip-mipi-csi2":4 []
<- "rockchip-mipi-csi2":5 []
<- "rockchip-mipi-csi2":6 []
<- "rockchip-mipi-csi2":7 [ENABLED]
<- "rockchip-mipi-csi2":8 []
- entity 29: rkcif_scale_ch3 (1 pad, 8 links)
type Node subtype V4L flags 0
device node name /dev/video7
pad0: Sink
<- "rockchip-mipi-csi2":1 []
<- "rockchip-mipi-csi2":2 []
<- "rockchip-mipi-csi2":3 []
<- "rockchip-mipi-csi2":4 []
<- "rockchip-mipi-csi2":5 []
<- "rockchip-mipi-csi2":6 []
<- "rockchip-mipi-csi2":7 []
<- "rockchip-mipi-csi2":8 [ENABLED]
- entity 33: rockchip-mipi-csi2 (9 pads, 65 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev0
pad0: Sink
fmt:SBGGR10_1X10/4224x3136 field:none crop.bounds:(0,0)/4224x3136 crop:(0,0)/4224x3136
<- "rockchip-csi2-dphy0":1 [ENABLED]
pad1: Source
-> "stream_cif_mipi_id0":0 [ENABLED]
-> "stream_cif_mipi_id1":0 []
-> "stream_cif_mipi_id2":0 []
-> "stream_cif_mipi_id3":0 []
-> "rkcif_scale_ch0":0 []
-> "rkcif_scale_ch1":0 []
-> "rkcif_scale_ch2":0 []
-> "rkcif_scale_ch3":0 []
pad2: Source
-> "stream_cif_mipi_id0":0 []
-> "stream_cif_mipi_id1":0 [ENABLED]
-> "stream_cif_mipi_id2":0 []
-> "stream_cif_mipi_id3":0 []
-> "rkcif_scale_ch0":0 []
-> "rkcif_scale_ch1":0 []
-> "rkcif_scale_ch2":0 []
-> "rkcif_scale_ch3":0 []
pad3: Source
-> "stream_cif_mipi_id0":0 []
-> "stream_cif_mipi_id1":0 []
-> "stream_cif_mipi_id2":0 [ENABLED]
-> "stream_cif_mipi_id3":0 []
-> "rkcif_scale_ch0":0 []
-> "rkcif_scale_ch1":0 []
-> "rkcif_scale_ch2":0 []
-> "rkcif_scale_ch3":0 []
pad4: Source
-> "stream_cif_mipi_id0":0 []
-> "stream_cif_mipi_id1":0 []
-> "stream_cif_mipi_id2":0 []
-> "stream_cif_mipi_id3":0 [ENABLED]
-> "rkcif_scale_ch0":0 []
-> "rkcif_scale_ch1":0 []
-> "rkcif_scale_ch2":0 []
-> "rkcif_scale_ch3":0 []
pad5: Source
-> "stream_cif_mipi_id0":0 []
-> "stream_cif_mipi_id1":0 []
-> "stream_cif_mipi_id2":0 []
-> "stream_cif_mipi_id3":0 []
-> "rkcif_scale_ch0":0 [ENABLED]
-> "rkcif_scale_ch1":0 []
-> "rkcif_scale_ch2":0 []
-> "rkcif_scale_ch3":0 []
pad6: Source
-> "stream_cif_mipi_id0":0 []
-> "stream_cif_mipi_id1":0 []
-> "stream_cif_mipi_id2":0 []
-> "stream_cif_mipi_id3":0 []
-> "rkcif_scale_ch0":0 []
-> "rkcif_scale_ch1":0 [ENABLED]
-> "rkcif_scale_ch2":0 []
-> "rkcif_scale_ch3":0 []
pad7: Source
-> "stream_cif_mipi_id0":0 []
-> "stream_cif_mipi_id1":0 []
-> "stream_cif_mipi_id2":0 []
-> "stream_cif_mipi_id3":0 []
-> "rkcif_scale_ch0":0 []
-> "rkcif_scale_ch1":0 []
-> "rkcif_scale_ch2":0 [ENABLED]
-> "rkcif_scale_ch3":0 []
pad8: Source
-> "stream_cif_mipi_id0":0 []
-> "stream_cif_mipi_id1":0 []
-> "stream_cif_mipi_id2":0 []
-> "stream_cif_mipi_id3":0 []
-> "rkcif_scale_ch0":0 []
-> "rkcif_scale_ch1":0 []
-> "rkcif_scale_ch2":0 []
-> "rkcif_scale_ch3":0 [ENABLED]
- entity 43: rockchip-csi2-dphy0 (2 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev1
pad0: Sink
fmt:SBGGR10_1X10/4224x3136@10000/300000 field:none crop.bounds:(0,0)/4224x3136
<- "m00_b_ov13855 3-0036":0 [ENABLED]
pad1: Source
-> "rockchip-mipi-csi2":0 [ENABLED]
- entity 48: m00_b_ov13855 3-0036 (1 pad, 1 link)
type V4L2 subdev subtype Sensor flags 0
device node name /dev/v4l-subdev2
pad0: Source
fmt:SBGGR10_1X10/4224x3136@10000/300000 field:none crop.bounds:(0,0)/4224x3136
-> "rockchip-csi2-dphy0":0 [ENABLED]
- entity 52: m00_b_vm149c 3-000c (0 pad, 0 link)
type V4L2 subdev subtype Lens flags 0
device node name /dev/v4l-subdev3
root@ok3588:/etc/iqfiles#
root@ok3588:/etc/iqfiles#
【摄像头介入CAM0】
4、另外您是预览的哪个video节点呢？
/dev/video0
/dev/video1
/dev/video2
/dev/video3
gst-launch-1.0 v4l2src device=/dev/video0 ! video/x-raw, format=NV12, width=3840,height=2160, framerate=30/1 ! waylandsink
/dev/video4
/dev/video5
/dev/video6
/dev/video7
【打开出错了】
5、打开摄像头之后的隐患排查：
914.097118\] rockchip-csi2-dphy csi2-dcphy0: csi2_dphy_update_sensor_mbus fail to get dphy param, used default value \[ 914.097124\] rockchip-csi2-dphy csi2-dcphy0: csi2_dphy_update_sensor_mbus fail to get dphy param, used default value 开关 飞凌开发板 附带的 OV13850。就会出现 警告信息。看字面 意思是在 驱动中更新 DPHY/MIPI的 信息失败了？请问 是啥原因呢？ ov13850在驱动中没有注册get_param函数，实际这个函数并不影响使用 Y:\\OK3588_Linux_fs\\kernel\\drivers\\phy\\rockchip\\phy-rockchip-csi2-dphy.c if (dphy-\>drv_data-\>vendor == PHY_VENDOR_SAMSUNG) { ret = v4l2_subdev_call(sensor_sd, core, ioctl, RKMODULE_GET_CSI_DPHY_PARAM, dphy-\>dphy_param); if (ret) { dev_info(dphy-\>dev, "%s fail to get dphy param, used default value\\n", __func__); ret = 0; } } 6、在Ubuntu下用ll命令习惯了，不想老是打ls -l，请问OK3588-C下如何增加 ll 命令呢？   Y:\\OK3588_Linux_fs\\kernel\\arch\\arm64\\boot\\dts\\rockchip\\OK3588-C-Camera.dtsi // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /\* \* Copyright (c) 2022 Forlinx Co., Ltd. \* \* rkisp0 --\> rkisp0_vir0/rkisp0_vir1/rkisp0_vir2/rkisp0_vir3 \* rkisp1 --\> rkisp1_vir0/rkisp1_vir1/rkisp1_vir2/rkisp1_vir3 \* rkcif_mipi_lvds --\> rkcif_mipi_lvds\[0-4\]_sditf \* mipicamera0 --\> csi2_dcphy0 --\> mipi0_csi2 --\>rkcif_mipi_lvds --\> rkcif_mipi_lvds_sditf --\> rkisp0_vir0 \* mipicamera1 --\> csi2_dcphy1 --\> mipi1_csi2 --\>rkcif_mipi_lvds1 --\> rkcif_mipi_lvds1_sditf --\> rkisp0_vir1 \* csi2_dphy0 or (csi2_dphy1、csi2_dphy2) dphy0 \* csi2_dphy3 or (csi2_dphy4、csi2_dphy5) dphy1 \* mipicamera2 --\> csi2_dphy1 --\> mipi2_csi2 --\>rkcif_mipi_lvds2 --\>rkcif_mipi_lvds2_sditf --\> rkisp0_vir2 \* mipicamera3 --\> csi2_dphy2 --\> mipi3_csi2 --\>rkcif_mipi_lvds3 --\>rkcif_mipi_lvds3_sditf --\> rkisp1_vir0 \* mipicamera4 --\> csi2_dphy4 --\> mipi4_csi2 --\>rkcif_mipi_lvds4 --\>rkcif_mipi_lvds4_sditf --\> rkisp1_vir1 \* mipicamera5 --\> csi2_dphy5 --\> mipi5_csi2 --\>rkcif_mipi_lvds5 --\>rkcif_mipi_lvds5_sditf --\> rkisp1_vir2 \* mipicamera6 --\> rkcif_dvp ---\> rkcif_dvp_sditf \*/ / { ext_cam_clk: external-camera-clock { compatible = "fixed-clock"; clock-frequency = \<24000000\>; clock-output-names = "CLK_CAMERA_24MHZ"; #clock-cells = \<0\>; }; }; \&rkcif { status = "okay"; }; \&rkcif_mmu { status = "okay"; }; //\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* //\*\*\* CAM1 OV13855 Configuration description \*\*\* //\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* \&mipi_dcphy0 { status = "okay"; }; \&rkisp1 { status = "okay"; }; \&isp1_mmu { status = "okay"; }; \&i2c3 { status = "okay"; clock-frequency = \<400000\>; vm149c_0: vm149c@0c { compatible = "silicon touch,vm149c"; status = "okay"; reg = \<0x0c\>; rockchip,camera-module-index = \<0\>; rockchip,camera-module-facing = "back"; }; cam1_ov13855: cam1_ov13855@36 { compatible = "ovti,ov13855"; status = "okay"; reg = \<0x36\>; clocks = \<\&ext_cam_clk\>; clock-names = "xvclk"; pwdn-gpios = \<\&extio EXTIO_GPIO_P01 GPIO_ACTIVE_HIGH\>; reset-gpios = \<\&extio EXTIO_GPIO_P00 GPIO_ACTIVE_HIGH\>; rockchip,camera-module-index = \<0\>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "forlinx"; rockchip,camera-module-lens-name = "default"; lens-focus = \<\&vm149c_0\>; port { cam1_ov13855_out: endpoint { remote-endpoint = \<\&mipi_in_0_ucam1\>; data-lanes = \<1 2 3 4\>; }; }; }; }; \&csi2_dcphy0 { status = "okay"; ports { #address-cells = \<1\>; #size-cells = \<0\>; port@0 { reg = \<0\>; #address-cells = \<1\>; #size-cells = \<0\>; mipi_in_0_ucam1: endpoint@1 { reg = \<1\>; remote-endpoint = \<\&cam1_ov13855_out\>; data-lanes = \<1 2 3 4\>; }; }; port@1 { reg = \<1\>; #address-cells = \<1\>; #size-cells = \<0\>; csidcphy0_out: endpoint@0 { reg = \<0\>; remote-endpoint = \<\&mipi0_csi2_input\>; }; }; }; }; \&mipi0_csi2 { status = "okay"; ports { #address-cells = \<1\>; #size-cells = \<0\>; port@0 { reg = \<0\>; #address-cells = \<1\>; #size-cells = \<0\>; mipi0_csi2_input: endpoint@0 { reg = \<0\>; remote-endpoint = \<\&csidcphy0_out\>; }; }; port@1 { reg = \<1\>; #address-cells = \<1\>; #size-cells = \<0\>; mipi0_csi2_output: endpoint@0 { reg = \<0\>; remote-endpoint = \<\&cif_mipi_lvds0\>; }; }; }; }; \&rkcif_mipi_lvds { status = "okay"; port { cif_mipi_lvds0: endpoint { remote-endpoint = \<\&mipi0_csi2_output\>; }; }; }; \&rkcif_mipi_lvds_sditf { status = "okay"; port { mipi_lvds_sditf: endpoint { remote-endpoint = \<\&isp1_in2\>; }; }; }; \&rkisp1_vir0 { status = "okay"; port { #address-cells = \<1\>; #size-cells = \<0\>; isp1_in2: endpoint@0 { reg = \<0\>; remote-endpoint = \<\&mipi_lvds_sditf\>; }; }; }; \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* \*\*\* CAM2 OV13850 Configuration description \*\*\* \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* // //\&mipi_dcphy1 { // status = "okay"; //}; // //\&i2c4 { // status = "okay"; // clock-frequency = \<400000\>; // // vm149c_1: vm149c@0c { // compatible = "silicon touch,vm149c"; // status = "okay"; // reg = \<0x0c\>; // rockchip,camera-module-index = \<1\>; // rockchip,camera-module-facing = "back"; // }; // // cam2_ov13850: cam2_ov13850@10 { // compatible = "ovti,ov13850"; // status = "okay"; // reg = \<0x10\>; // // clocks = \<\&ext_cam_clk\>; // clock-names = "xvclk"; // // pwdn-gpios = \<\&extio EXTIO_GPIO_P03 GPIO_ACTIVE_HIGH\>; // reset-gpios = \<\&extio EXTIO_GPIO_P02 GPIO_ACTIVE_HIGH\>; // rockchip,camera-module-index = \<1\>; // rockchip,camera-module-facing = "front"; // rockchip,camera-module-name = "forlinx"; // rockchip,camera-module-lens-name = "default"; // lens-focus = \<\&vm149c_1\>; // // port { // cam2_ov13850_out: endpoint { // remote-endpoint = \<\&mipi_in_1_ucam2\>; // data-lanes = \<1 2\>; // }; // }; // }; //}; // //\&csi2_dcphy1 { // status = "okay"; // ports { // #address-cells = \<1\>; // #size-cells = \<0\>; // port@0 { // reg = \<0\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi_in_1_ucam2: endpoint@1 { // reg = \<1\>; // remote-endpoint = \<\&cam2_ov13850_out\>; // data-lanes = \<1 2\>; // }; // }; // port@1 { // reg = \<1\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // csidcphy1_out: endpoint@0 { // reg = \<0\>; // remote-endpoint = \<\&mipi1_csi2_input\>; // }; // }; // }; //}; // //\&mipi1_csi2 { // status = "okay"; // ports { // #address-cells = \<1\>; // #size-cells = \<0\>; // port@0 { // reg = \<0\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi1_csi2_input: endpoint@1 { // reg = \<1\>; // remote-endpoint = \<\&csidcphy1_out\>; // }; // }; // port@1 { // reg = \<1\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi1_csi2_output: endpoint@0 { // reg = \<0\>; // remote-endpoint = \<\&cif_mipi_lvds1\>; // }; // }; // }; //}; // //\&rkcif_mipi_lvds1 { // status = "okay"; // port { // cif_mipi_lvds1: endpoint { // remote-endpoint = \<\&mipi1_csi2_output\>; // }; // }; //}; // //\&rkcif_mipi_lvds1_sditf { // status = "okay"; // port { // mipi_lvds1_sditf: endpoint { // remote-endpoint = \<\&isp0_vir1\>; // }; // }; //}; // //\&rkisp0_vir1 { // status = "okay"; // port { // #address-cells = \<1\>; // #size-cells = \<0\>; // isp0_vir1: endpoint@0 { // reg = \<0\>; // remote-endpoint = \<\&mipi_lvds1_sditf\>; // }; // }; //}; // \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* \*\*\* CAM3 OV5645 Configuration Description \*\*\*\* \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* // //\&csi2_dphy0_hw { // status = "okay"; //}; // //\&i2c7 { // status = "okay"; // clock-frequency = \<400000\>; // // cam3_ov5645: cam3_ov5645@3c { // compatible = "ovti,ov5645"; // status = "okay"; // reg = \<0x3c\>; // // clocks = \<\&ext_cam_clk\>; // clock-names = "xclk"; // clock-frequency = \<24000000\>; // // enable-gpios = \<\&extio EXTIO_GPIO_P05 GPIO_ACTIVE_HIGH\>; // reset-gpios = \<\&extio EXTIO_GPIO_P04 GPIO_ACTIVE_LOW\>; // rockchip,camera-module-index = \<0\>; // rockchip,camera-module-facing = "back"; // rockchip,camera-module-name = "NC"; // rockchip,camera-module-lens-name = "NC"; // // port { // cam3_ov5645_out: endpoint { // remote-endpoint = \<\&mipi_in_ucam3\>; // data-lanes = \<1 2\>; // }; // }; // }; //}; // //\&csi2_dphy0 { // status = "okay"; // ports { // #address-cells = \<1\>; // #size-cells = \<0\>; // port@0 { // reg = \<0\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi_in_ucam3: endpoint@1 { // reg = \<1\>; // remote-endpoint = \<\&cam3_ov5645_out\>; // data-lanes = \<1 2\>; // }; // }; // port@1 { // reg = \<1\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi2_csi2_mipicsi0_out0: endpoint@0 { // reg = \<0\>; // remote-endpoint = \<\&mipi2_csi2_input\>; // }; // }; // }; //}; // //\&mipi2_csi2 { // status = "okay"; // ports { // #address-cells = \<1\>; // #size-cells = \<0\>; // port@0 { // reg = \<0\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi2_csi2_input: endpoint@1 { // reg = \<1\>; // remote-endpoint = \<\&mipi2_csi2_mipicsi0_out0\>; // }; // }; // port@1 { // reg = \<1\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi2_csi2_output: endpoint@0 { // reg = \<0\>; // remote-endpoint = \<\&cif_mipi_lvds2\>; // }; // }; // }; //}; // //\&rkcif_mipi_lvds2 { // status = "okay"; // port { // cif_mipi_lvds2: endpoint { // remote-endpoint = \<\&mipi2_csi2_output\>; // }; // }; //}; // //\&rkcif_mipi_lvds2_sditf { // status = "disabled"; //}; // \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* \*\*\* CAM4 OV5645 Configuration Description \*\*\*\* \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* // //\&csi2_dphy1_hw { // status = "okay"; //}; // //\&i2c3 { // status = "okay"; // // cam4_ov5645: cam4_ov5645@3c { // status = "okay"; // compatible = "ovti,ov5645"; // reg = \<0x3c\>; // clocks = \<\&ext_cam_clk\>; // clock-names = "xclk"; // clock-frequency = \<24000000\>; // // reset-gpios = \<\&extio EXTIO_GPIO_P06 GPIO_ACTIVE_LOW\>; // enable-gpios = \<\&extio EXTIO_GPIO_P07 GPIO_ACTIVE_HIGH\>; // // rockchip,camera-module-index = \<1\>; // rockchip,camera-module-facing = "front"; // rockchip,camera-module-name = "NC"; // rockchip,camera-module-lens-name = "NC"; // port { // cam4_ov5645_out: endpoint { // remote-endpoint = \<\&mipi_in_ucam4\>; // data-lanes = \<1 2\>; // }; // }; // }; //}; // //\&csi2_dphy4 { // status = "okay"; // ports { // #address-cells = \<1\>; // #size-cells = \<0\>; // port@0 { // reg = \<0\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi_in_ucam4: endpoint@1 { // reg = \<1\>; // remote-endpoint = \<\&cam4_ov5645_out\>; // data-lanes = \<1 2\>; // }; // }; // port@1 { // reg = \<1\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi4_csi2_csidphy1_out0: endpoint@0 { // reg = \<0\>; // remote-endpoint = \<\&mipi4_csi2_input\>; // }; // }; // }; //}; // //\&mipi4_csi2 { // status = "okay"; // ports { // #address-cells = \<1\>; // #size-cells = \<0\>; // port@0 { // reg = \<0\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi4_csi2_input: endpoint@1 { // reg = \<1\>; // remote-endpoint = \<\&mipi4_csi2_csidphy1_out0\>; // }; // }; // port@1 { // reg = \<1\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi4_csi2_output: endpoint@0 { // reg = \<0\>; // remote-endpoint = \<\&cif_mipi_in4\>; // }; // }; // }; //}; // //\&rkcif_mipi_lvds4 { // status = "okay"; // port { // cif_mipi_in4: endpoint { // remote-endpoint = \<\&mipi4_csi2_output\>; // }; // }; //}; // //\&rkcif_mipi_lvds4_sditf { // status = "disabled"; //}; // \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* \*\*\* CAM5 OV5645 Configuration Description \*\*\*\* \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* // //\&i2c4 { // status = "okay"; // // cam5_ov5645: cam5_ov5645@3c { // status = "okay"; // compatible = "ovti,ov5645"; // reg = \<0x3c\>; // clocks = \<\&ext_cam_clk\>; // clock-names = "xclk"; // clock-frequency = \<24000000\>; // // reset-gpios = \<\&extio EXTIO_GPIO_P10 GPIO_ACTIVE_LOW\>; // enable-gpios = \<\&extio EXTIO_GPIO_P11 GPIO_ACTIVE_HIGH\>; // // rockchip,camera-module-index = \<2\>; // rockchip,camera-module-facing = "front"; // rockchip,camera-module-name = "NC"; // rockchip,camera-module-lens-name = "NC"; // port { // cam5_ov5645_out: endpoint { // remote-endpoint = \<\&mipi_in_ucam5\>; // data-lanes = \<1 2\>; // }; // }; // }; //}; // //\&csi2_dphy5 { // status = "okay"; // ports { // #address-cells = \<1\>; // #size-cells = \<0\>; // port@0 { // reg = \<0\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi_in_ucam5: endpoint@1 { // reg = \<1\>; // remote-endpoint = \<\&cam5_ov5645_out\>; // data-lanes = \<1 2\>; // }; // }; // port@1 { // reg = \<1\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi5_csi2_csidphy1_out1: endpoint@0 { // reg = \<0\>; // remote-endpoint = \<\&mipi5_csi2_input\>; // }; // }; // }; //}; // //\&mipi5_csi2 { // status = "okay"; // ports { // #address-cells = \<1\>; // #size-cells = \<0\>; // port@0 { // reg = \<0\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi5_csi2_input: endpoint@1 { // reg = \<1\>; // remote-endpoint = \<\&mipi5_csi2_csidphy1_out1\>; // }; // }; // port@1 { // reg = \<1\>; // #address-cells = \<1\>; // #size-cells = \<0\>; // mipi5_csi2_output: endpoint@0 { // reg = \<0\>; // remote-endpoint = \<\&cif_mipi_in5\>; // }; // }; // }; //}; // //\&rkcif_mipi_lvds5 { // status = "okay"; // port { // cif_mipi_in5: endpoint { // remote-endpoint = \<\&mipi5_csi2_output\>; // }; // }; //}; // //\&rkcif_mipi_lvds5_sditf { // status = "disabled"; //};