-combinational英文示意- Specifies that the source latency paths for this type of generated clock only includes the logic where the master clock propagates along combinational paths. The source latency paths will not flow through sequential element clock pins, transparent latch data pins, or the source pins of other generated clocks.
-combinational中文翻译:
"指定这种类型的generated_clock的source latency只包括主时钟通过组合逻辑传播的路径。source latency不会通过以下几种情况:
- 时序元件的时钟引脚,
- 透明锁存器的数据引脚,
- 其他 generated_clock的源引脚。"
简而言之,source latency只计算主时钟在组合逻辑中的传播时间,而不会包含任何经过时序元件(如触发器或锁存器)或其他派生时钟的路径。