https://zhuanlan.zhihu.com/p/580037903?utm_id=0
ug994
-- Normally AXI is automatically inferred. However, if the names of your ports do not match, you can force the
-- the creation of an interface and map the physical ports to the logical ports by using the X_INTERFACE_INFO
-- attribute before each physical port
-- Parameters are typically computed by the Block Diagram and annotated onto the cell (no need to specify these)
-- axis - AMBA AXI4-Stream Interface (slave directions)
--
-- Allowed parameters:
-- CLK_DOMAIN - Clk Domain (string default: <blank>)
-- PHASE - Phase (float)
-- FREQ_HZ - Frequency (float default: 100000000)
-- LAYERED_METADATA - Layered Metadata (string default: <blank>)
-- HAS_TLAST - Has Tlast (long) {false - 0, true - 1}
-- HAS_TKEEP - Has Tkeep (long) {false - 0, true - 1}
-- HAS_TSTRB - Has Tstrb (long) {false - 0, true - 1}
-- HAS_TREADY - Has Tready (long) {false - 0, true - 1}
-- TUSER_WIDTH - Tuser Width (long)
-- TID_WIDTH - Tid Width (long)
-- TDEST_WIDTH - Tdest Width (long)
-- TDATA_NUM_BYTES - Tdata Num Bytes (long)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity my_module is
port (
<s_tid> : in std_logic_vector(<left_bound> downto 0); -- Transfer ID tag (optional)
<s_tdest> : in std_logic_vector(<left_bound> downto 0); -- Transfer Destination (optional)
<s_tdata> : in std_logic_vector(<left_bound> downto 0); -- Transfer Data (optional)
<s_tstrb> : in std_logic_vector(<left_bound> downto 0); -- Transfer Data Byte Strobes (optional)
<s_tkeep> : in std_logic_vector(<left_bound> downto 0); -- Transfer Null Byte Indicators (optional)
<s_tlast> : in std_logic; -- Packet Boundary Indicator (optional)
<s_tuser> : in std_logic_vector(<left_bound> downto 0); -- Transfer user sideband (optional)
<s_tvalid> : in std_logic; -- Transfer valid (required)
<s_tready> : out std_logic; -- Transfer ready (optional)
-- additional ports here
);
end my_module;
architecture arch_impl of my_module is
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of <s_tid>: SIGNAL is "xilinx.com:interface:axis:1.0 <interface_name> TID";
ATTRIBUTE X_INTERFACE_INFO of <s_tdest>: SIGNAL is "xilinx.com:interface:axis:1.0 <interface_name> TDEST";
ATTRIBUTE X_INTERFACE_INFO of <s_tdata>: SIGNAL is "xilinx.com:interface:axis:1.0 <interface_name> TDATA";
ATTRIBUTE X_INTERFACE_INFO of <s_tstrb>: SIGNAL is "xilinx.com:interface:axis:1.0 <interface_name> TSTRB";
ATTRIBUTE X_INTERFACE_INFO of <s_tkeep>: SIGNAL is "xilinx.com:interface:axis:1.0 <interface_name> TKEEP";
ATTRIBUTE X_INTERFACE_INFO of <s_tlast>: SIGNAL is "xilinx.com:interface:axis:1.0 <interface_name> TLAST";
ATTRIBUTE X_INTERFACE_INFO of <s_tuser>: SIGNAL is "xilinx.com:interface:axis:1.0 <interface_name> TUSER";
ATTRIBUTE X_INTERFACE_INFO of <s_tvalid>: SIGNAL is "xilinx.com:interface:axis:1.0 <interface_name> TVALID";
ATTRIBUTE X_INTERFACE_INFO of <s_tready>: SIGNAL is "xilinx.com:interface:axis:1.0 <interface_name> TREADY";
-- Uncomment the following to set interface specific parameter on the bus interface.
-- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
-- ATTRIBUTE X_INTERFACE_PARAMETER of <port_name>: SIGNAL is "CLK_DOMAIN <value>,PHASE <value>,FREQ_HZ <value>,LAYERED_METADATA <value>,HAS_TLAST <value>,HAS_TKEEP <value>,HAS_TSTRB <value>,HAS_TREADY <value>,TUSER_WIDTH <value>,TID_WIDTH <value>,TDEST_WIDTH <value>,TDATA_NUM_BYTES <value>";
begin
-- user logic here