在修改完logisim电路文件后,就可以将其转化为verilog项目了。
- 点击"Save Verilog",弹出Logisim转Verilog对话框,在该对话框中完成4个选项的设置。(注意输出地址不为中文路径)
- 在转换时发现"元件RegisterFile不支持HDL转换",这时我们需要将
Regfile
电路的Register File
元件删掉,并在以后的verilog文件中重写Regfile。 - 转
换成功后,在
Verilog/circuit/路径中修改
Regifile.v`文件,具体内容如下:
verilog
/******************************************************************************
** Logisim goes FPGA automatic generated Verilog code **
** **
** Component : regifile **
** **
******************************************************************************/
`timescale 1ns/1ps
module regifile( Clk,
Din,
LOGISIM_CLOCK_TREE_0,
R1Adr,
R2Adr,
WAdr,
WE,
R1,
R2);
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input Clk;
input[31:0] Din;
input[4:0] LOGISIM_CLOCK_TREE_0;
input[4:0] R1Adr;
input[4:0] R2Adr;
input[4:0] WAdr;
input WE;
/***************************************************************************
** Here the outputs are defined **
***************************************************************************/
output[31:0] R1;
output[31:0] R2;
reg [31:0]register[31:0];
assign R1=register[R1Adr];
assign R2=register[R2Adr];
always@(negedge Clk)
begin
if(WE==1)
register[WAdr]<=Din;
register[0]<=0;
end
endmodule
-
在生成的verilog项目的文件夹中找到文件
mips_cpu_project.tcl
(或其他名称的.tcl文件)。打开vivado,在页面下方点击Tcl Console
,在输入命令行 的地方输入cd + .Tcl所在的路径名,如C:/xxx,然后输入source+.tcl的文件名,即可自动生成项目。具体如下(以mips_cpu_project.tcl
为例):cd D:\Xilinx\z_computerhardware\toverilog\cpu21-riscv\single_cycle_MIPS
source mips_cpu_project.tcl
- 修改
LogisimToplevelShell.xdc
文件,进行接口绑定。具体修改如下:
verilog
##Clock signal
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { FPGA_GlobalClock }];
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {FPGA_GlobalClock}];
##Switches
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { FPGA_INPUT_PIN_0 }];
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { FPGA_INPUT_PIN_1 }];
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { FPGA_INPUT_PIN_2 }];
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }];
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { set_second }];
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }];
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }];
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }];
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { set_minute }];
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }];
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }];
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }];
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { set_hour }];
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }];
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }];
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { rst }];
##LEDs
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { done }];
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }];
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }];
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }];
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { second_led }];
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }];
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }];
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }];
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { minute_led }];
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }];
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }];
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }];
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { hour_led }];
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }];
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }];
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { time_tick }];
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }];
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }];
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }];
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }];
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }];
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }];
##7 segment display
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[7] }];
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[6] }];
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[5] }];
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[4] }];
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[3] }];
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[2] }];
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[1] }];
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[0] }];
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[0] }];
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[1] }];
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[2] }];
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[3] }];
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[4] }];
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[5] }];
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[6] }];
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { FPGA_OUTPUT_PIN_1[7] }];
##Buttons
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { rst_n }];
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { start }];
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { Button[2] }];
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { Button[3] }];
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { Button[4] }];
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { Button[5] }];
- 添加顶层封装文件
LogisimToplevelShell.v
,负责对接5个输入输出引脚(时钟、RST、Go以及两个FPGADigit的两个输出)。其内容如下:
verilog
module LogisimToplevelShell(
FPGA_GlobalClock,
FPGA_INPUT_PIN_0,
FPGA_INPUT_PIN_1,
FPGA_OUTPUT_PIN_0,
FPGA_OUTPUT_PIN_1,
);
assign FPGA_INPUT_PIN_0 = NA;
assign FPGA_INPUT_PIN_1 = SEG;
assign RST = FPGA_INPUT_PIN_0;
assign Go_signal = FPGA_INPUT_PIN_1;
endmodule
- 完成以上操作之后,就可以按照verilog的上板步骤进行上板了。
END