ZYNQ PS和PL交互

文章目录

[ZYNQ PS和PL交互](#ZYNQ PS和PL交互)
前言
一、交互方式
- [1.1 GP接口](#1.1 GP接口)
- [1.2 PS AXI_MASTER](#1.2 PS AXI_MASTER)
- [1.3 PS AXI_SLAVE](#1.3 PS AXI_SLAVE)
- [1.4 HP接口和ACP接口](#1.4 HP接口和ACP接口)
[二 GP接口应用](#二 GP接口应用)

前言

一、交互方式

1.1 GP接口

AXIM_GP:属于AXI-lite协议。适用于少量数据

一般不用AXI-FIFO作为数据交互，因为互联模块本身也有FIFO（但是空间小）。大量数据其实也就不用这种方式。

1.2 PS AXI_MASTER

1.3 PS AXI_SLAVE

1.4 HP接口和ACP接口

适用快速、大量数据传输交互

二 GP接口应用

使用一个GP接口实现对PL端的BRAM的读写
Vivado Block Memory Generator v8.4学习总结
 GP接口
 通过BRAM实现PS与PL数据交互

代码如下：

c 复制代码

`timescale 1ns / 1ps

module RAM_WR#(
    parameter       P_OPERATION_NUM = 40    ,
    parameter       P_DATA_WIDTH    = 32    ,
    parameter       P_WRITE_BASEADDR= 0     ,
    parameter       P_READ_BASEADDR = 40    
)(
    input           i_clk           ,
    input           i_rst           ,

    output [31:0]   o_bram_addr     ,
    output [31:0]   o_bram_data     ,
    output          o_bram_en       ,
    output          o_bram_wen      ,
    input  [31:0]   i_bram_data      
);

localparam          P_BURST_LEN = P_OPERATION_NUM/(P_DATA_WIDTH/8);

reg  [31:0]         ro_bram_addr    ;
reg  [31:0]         ro_bram_data    ;
reg                 ro_bram_en      ;
reg                 ro_bram_wen     ;
reg  [15:0]         r_cnt           ;

assign o_bram_addr = ro_bram_addr   ;
assign o_bram_data = ro_bram_data   ;
assign o_bram_en   = ro_bram_en     ;
assign o_bram_wen  = ro_bram_wen    ;

always@(posedge i_clk,posedge i_rst)
begin
    if(i_rst)
        r_cnt <= 'd0;
    else if(r_cnt == 1000)
        r_cnt <= 'd0;
    else 
        r_cnt <= r_cnt + 1;
end

always@(posedge i_clk,posedge i_rst)
begin
    if(i_rst) begin
        ro_bram_addr <= 'd0;
        ro_bram_data <= 'd0;
        ro_bram_en   <= 'd0;
        ro_bram_wen  <= 'd0;
    end else if(r_cnt >= 100 && r_cnt < 100 + P_BURST_LEN) begin
        ro_bram_addr <= P_WRITE_BASEADDR + ((r_cnt - 100) << 2);
        ro_bram_data <= r_cnt - 100;
        ro_bram_en   <= 'd1;
        ro_bram_wen  <= 'd1;
    end else if(r_cnt >= 800 && r_cnt < 800 + P_BURST_LEN) begin
        ro_bram_addr <= P_READ_BASEADDR + ((r_cnt - 800) << 2);
        ro_bram_data <= 'd0;
        ro_bram_en   <= 'd1;
        ro_bram_wen  <= 'd0;
    end else begin
        ro_bram_addr <= 'd0;
        ro_bram_data <= 'd0;
        ro_bram_en   <= 'd0;
        ro_bram_wen  <= 'd0;
    end
end

`ifdef RAM_WR_ILA
ILAx5_32_32_1_1_32 ILAx5_32_32_1_1_32_u0 (
	.clk            (i_clk          ),      
	.probe0         (ro_bram_addr   ),   
	.probe1         (ro_bram_data   ),   
	.probe2         (ro_bram_en     ),   
	.probe3         (ro_bram_wen    ),   
	.probe4         (i_bram_data    )    
);
`endif

endmodule