概述
本文主要描述了在Qemu平台中，如何添加STM32F103的AFIO控制器模拟代码，AFIO是属于GPIO引脚复用配置的功能。
参考资料
STM32F1XX TRM手册，手册编号：RM0008
添加步骤
1、在hw/arm/Kconfig文件中添加STM32F1XX_AFIO，如下所示:
+号部分为新增加内容
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 2a66ff5f..c0edade0 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -419,6 +419,7 @@ config STM32F103_SOC
select STM32F1XX_FLASH
select STM32F1XX_USART
select STM32F1XX_GPIO
+ select STM32F1XX_AFIO2、在include/hw/arm/stm32f103_soc.h文件中添加
+号部分为新增加内容
diff --git a/include/hw/arm/stm32f103_soc.h b/include/hw/arm/stm32f103_soc.h
index c4c9bc52..ee015939 100644
--- a/include/hw/arm/stm32f103_soc.h
+++ b/include/hw/arm/stm32f103_soc.h
@@ -29,6 +29,7 @@
#include "hw/misc/stm32f1xx_flash.h"
#include "hw/char/stm32f1xx_usart.h"
#include "hw/gpio/stm32f1xx_gpio.h"
+#include "hw/misc/stm32f1xx_afio.h"
#define RCC_BASE_ADDR 0x40021000
#define EXTI_BASE_ADDR 0x40010400
@@ -40,14 +41,16 @@
#define UART2_BASE_ADDR 0x40004400
#define UART3_BASE_ADDR 0x40004800
+#define STM_AFIO_BASE 0x40010000
#define TYPE_STM32F103_SOC "stm32f103-soc"
#define STM32F103_SOC(obj) \
@@ -68,6 +71,7 @@ typedef struct STM32F103State {
STM32F1XXFlashState flash;
STM32F1XXUsartState usart[STM_NUM_USARTS];
STM32F1XXGPIOState gpio[STM_NUM_GPIOS];
+ STM32F1XXAFIOState afio;
} STM32F103State;3、在hw/arm/stm32f103_soc.c文件中添加如下代码片段
+号部分为新增加内容
diff --git a/hw/arm/stm32f103_soc.c b/hw/arm/stm32f103_soc.c
index d673eace..f9f0c120 100644
--- a/hw/arm/stm32f103_soc.c
+++ b/hw/arm/stm32f103_soc.c
@@ -72,6 +72,9 @@ static void stm32f103_soc_initfn(Object *obj)
sysbus_init_child_obj(obj, "flash", &s->flash, sizeof(s->flash),
TYPE_STM32F1XX_FLASH);
+ sysbus_init_child_obj(obj, "afio", &s->afio, sizeof(s->afio),
+ TYPE_STM32F1XX_AFIO);
+
for (i = 0; i < STM_NUM_USARTS; i++) {
object_initialize(&s->usart[i], sizeof(s->usart[i]), TYPE_STM32F1XX_USART);
qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
@@ -167,6 +170,15 @@ static void stm32f103_soc_realize(DeviceState *dev_soc, Error **errp)
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, gpio_addr[i]);
}
+ /* AFIO Controller */
+ dev = DEVICE(&s->afio);
+ object_property_set_bool(OBJECT(&s->afio), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, STM_AFIO_MAPR2);
}
static Property stm32f103_soc_properties[] = {4.在hw/misc/Kconfig中添加
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index af2c8f8b..d140a18a 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -113,6 +113,9 @@ config STM32F1XX_PWR
config STM32F1XX_FLASH
bool
+config STM32F1XX_AFIO
+ bool
+
config STM32F2XX_SYSCFG
bool5.在hw/misc/Makefile.objs中添加
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index ec738e27..743d2b83 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -69,6 +69,7 @@ common-obj-$(CONFIG_STM32F1XX_RCC) += stm32f1xx_rcc.o
common-obj-$(CONFIG_STM32F1XX_EXTI) += stm32f1xx_exti.o
common-obj-$(CONFIG_STM32F1XX_PWR) += stm32f1xx_pwr.o
common-obj-$(CONFIG_STM32F1XX_FLASH) += stm32f1xx_flash.o
+common-obj-$(CONFIG_STM32F1XX_AFIO) += stm32f1xx_afio.o
obj-$(CONFIG_STM32F4XX_RCC) += stm32f4xx_rcc.o
obj-$(CONFIG_STM32F4XX_PWR) += stm32f4xx_pwr.o
obj-$(CONFIG_STM32F4XX_FLASH) += stm32f4xx_flash.o6.在hw/misc/创建新文件hw/misc/stm32f1xx_afio.c
+/*
+ * Copyright (c) 2025 liang yan <[email protected]>
+ *
+ * STM32F1XX AFIO
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "hw/misc/stm32f1xx_afio.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "qemu/module.h"
+
+#ifndef STM_AFIO_ERR_DEBUG
+#define STM_AFIO_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (STM_AFIO_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f1xx_afio_reset(DeviceState *dev)
+{
+ STM32F1XXAFIOState *s = STM32F1XX_AFIO(dev);
+ s->afio_evcr = 0x00000000;
+ s->afio_mapr = 0x00000000;
+ s->afio_exticr1 = 0x00000000;
+ s->afio_exticr2 = 0x00000000;
+ s->afio_exticr3 = 0x00000000;
+ s->afio_exticr4 = 0x00000000;
+ s->afio_mapr2 = 0x00000000;
+}
+
+static uint64_t stm32f1xx_afio_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ STM32F1XXAFIOState *s = opaque;
+ uint64_t retvalue = 0;
+
+ DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);
+ switch(addr) {
+ case STM_AFIO_EVCR:
+ retvalue = s->afio_evcr;
+ break;
+ case STM_AFIO_MAPR:
+ retvalue = s->afio_mapr;
+ break;
+ case STM_AFIO_EXTICR1:
+ retvalue = s->afio_exticr1;
+ break;
+ case STM_AFIO_EXTICR2:
+ retvalue = s->afio_exticr2;
+ break;
+ case STM_AFIO_EXTICR3:
+ retvalue = s->afio_exticr3;
+ break;
+ case STM_AFIO_EXTICR4:
+ retvalue = s->afio_exticr4;
+ break;
+ case STM_AFIO_MAPR2:
+ retvalue = s->afio_mapr2;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ retvalue = 0;
+ break;
+ }
+ return retvalue;
+}
+
+static void stm32f1xx_afio_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ STM32F1XXAFIOState *s = opaque;
+ uint32_t value = val64;
+
+ DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", addr, value);
+ switch(addr) {
+ case STM_AFIO_EVCR:
+ s->afio_evcr = value;
+ break;
+ case STM_AFIO_MAPR:
+ s->afio_mapr = value;
+ break;
+ case STM_AFIO_EXTICR1:
+ s->afio_exticr1 = value;
+ break;
+ case STM_AFIO_EXTICR2:
+ s->afio_exticr2 = value;
+ break;
+ case STM_AFIO_EXTICR3:
+ s->afio_exticr3 = value;
+ break;
+ case STM_AFIO_EXTICR4:
+ s->afio_exticr4 = value;
+ break;
+ case STM_AFIO_MAPR2:
+ s->afio_mapr2 = value;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ }
+}
+
+static const MemoryRegionOps stm32f1xx_afio_ops = {
+ .read = stm32f1xx_afio_read,
+ .write = stm32f1xx_afio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_stm32f1xx_afio = {
+ .name = TYPE_STM32F1XX_AFIO,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(afio_evcr, STM32F1XXAFIOState),
+ VMSTATE_UINT32(afio_mapr, STM32F1XXAFIOState),
+ VMSTATE_UINT32(afio_exticr1, STM32F1XXAFIOState),
+ VMSTATE_UINT32(afio_exticr2, STM32F1XXAFIOState),
+ VMSTATE_UINT32(afio_exticr3, STM32F1XXAFIOState),
+ VMSTATE_UINT32(afio_exticr4, STM32F1XXAFIOState),
+ VMSTATE_UINT32(afio_mapr2, STM32F1XXAFIOState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void stm32f1xx_afio_init(Object *obj)
+{
+ STM32F1XXAFIOState *s = STM32F1XX_AFIO(obj);
+
+ memory_region_init_io(&s->mmio, obj, &stm32f1xx_afio_ops, s,
+ TYPE_STM32F1XX_AFIO, 0x400);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+}
+
+static void stm32f1xx_afio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = stm32f1xx_afio_reset;
+ dc->vmsd = &vmstate_stm32f1xx_afio;
+}
+
+static const TypeInfo stm32f1xx_afio_info = {
+ .name = TYPE_STM32F1XX_AFIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32F1XXAFIOState),
+ .instance_init = stm32f1xx_afio_init,
+ .class_init = stm32f1xx_afio_class_init,
+};
+
+static void stm32f1xx_afio_register_types(void)
+{
+ type_register_static(&stm32f1xx_afio_info);
+}
+
+type_init(stm32f1xx_afio_register_types)7.在include/hw/misc/创建stm32f1xx_afio.h文件
+/*
+ * Copyright (c) 2025- liang yan <[email protected]>
+ *
+ * STM32F1XX AFIO
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+#ifndef STM32F1XX_AFIO_H
+#define STM32F1XX_AFIO_H
+
+#include "hw/sysbus.h"
+
+#define STM_AFIO_EVCR 0x00
+#define STM_AFIO_MAPR 0x04
+#define STM_AFIO_EXTICR1 0x08
+#define STM_AFIO_EXTICR2 0x0c
+#define STM_AFIO_EXTICR3 0x10
+#define STM_AFIO_EXTICR4 0x14
+#define STM_AFIO_MAPR2 0x1c
+
+#define TYPE_STM32F1XX_AFIO "stm32f1xx-afio"
+#define STM32F1XX_AFIO(obj) \
+ OBJECT_CHECK(STM32F1XXAFIOState, (obj), TYPE_STM32F1XX_AFIO)
+
+typedef struct {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint32_t afio_evcr;
+ uint32_t afio_mapr;
+ uint32_t afio_exticr1;
+ uint32_t afio_exticr2;
+ uint32_t afio_exticr3;
+ uint32_t afio_exticr4;
+ uint32_t afio_mapr2;
+
+
+ qemu_irq irq;
+
+} STM32F1XXAFIOState;
+
+#endif总结
本文描述了如何在qemu中添加stm32f103平台上AFIO控制器实现步骤。