FPGA编译问题大集合：
问题：* Error (suppressible): (vsim-3053) D:/TestProFPGA/verilog_test/flow_led/sim/tb/flow_led_tb.v(19): Illegal output or inout port connection for port 'led'.
Time: 0 ns Iteration: 0 Instance: /flow_led_tb/u0_flow_led File: D:/TestProFPGA/verilog_test/flow_led/rtl/flow_led.v
输出信号led，在被测模块中为 reg [3:0] led，但是 testBench文件中应该声明： wire [3:0] led，调用写好的模块（被测不改） 。
问题：* Error: D:workspaceModelSimwork flow_led_tb.v(1): near "'t": Illegal base specifier in numeric constant.
** Error: D:workspaceModelSimwork flow_led_tb.v(1): near "'t": syntax error, unexpected BASE, expecting class
timescale左上角的一点是数字键1的左边那个键的点，而不是双引号的点。