TVM / IREE 的真实调度器架构
TVM 调度器架构图（TVM Relay → TIR → Target IR）
TVM 有两个调度路径：
- 手写 schedule（TIR）
- 自动调度（AutoTVM / AutoScheduler Ansor）
两条路径最终都生成 TIR → Lower → LLVM/CUDA/Metal。
TVM 编译全栈架构图（含调度）
+-------------------------------------------------------------+
| Relay IR |
| (High-level graph: Conv2D, MatMul, Add, etc.) |
+-------------------------------------------------------------+
| Graph-level passes (Fuse / InferType)
v
+-------------------------------------------------------------+
| Relay -> TIR Lowering (Op Strategy) |
| 选择算子实现 + Compute DAG + Layout transform |
+-------------------------------------------------------------+
|
(进入调度阶段)
|
+----------------------------------------+
| Schedule 层 |
+----------------------------------------+
| 手写 TIR schedule | AutoTVM (SA) |
| (compute_at, tile) | AutoScheduler |
| | (Sketch + GA) |
+----------------------------------------+
| TIR IR (Optimized Kernel IR)
v
+-------------------------------------------------------------+
| Lower TIR → TEIR → PrimFunc |
+-------------------------------------------------------------+
|
v
+-------------------------------------------------------------+
| Target Lowering (LLVM / CUDA / Metal / Hexagon) |
+-------------------------------------------------------------+TVM 调度层（Schedule Layer）细节图
+---------------------------+
| compute_dag |
+---------------------------+
|
+---------------------------+
| Schedule Search Space |
| (tile/split/reorder...) |
+---------------------------+
|
+---------------------------------------------------+
| 两类调度路径 |
+----------------------+----------------------------+
| 手写调度（TIR） | Auto 调度（Ansor / AutoTVM） |
+----------------------+----------------------------+
| Rule-based: | AutoTVM: SA + Cost Model |
| compute_at | AutoScheduler(Ansor): |
| fuse | - Sketch |
| vectorize | - Evolutionary Search |
| unroll | - ML Cost Model |
+----------------------+----------------------------+
|
TIR PrimFuncTVM 的调度核心就是：
在 TIR 层进行 kernel-level schedule，再把 PrimFunc 降到 target backend。
IREE 调度器架构图（StableHLO → Linalg → HAL → LLVM/VMVX/Vulkan）
IREE 的调度结构完全基于 MLIR，不依赖搜索。
它是 规则型（Rule-based）流水线。
IREE 编译全栈（含调度）架构图
+--------------------------------------------------------------+
| StableHLO / MHLO / TOSA (High-level) |
+--------------------------------------------------------------+
| HLO passes (Fusion / Canonicalize)
v
+--------------------------------------------------------------+
| Linalg on tensors (核心调度层) |
+--------------------------------------------------------------+
|
+----------------------------------+
| Linalg -> Loop / Tiling passes |
+----------------------------------+
| - Tile and Fuse |
| - Vectorize |
| - Unroll |
| - Bufferization |
+----------------------------------+
v
+--------------------------------------------------------------+
| Flow/HAL IR (执行时资源描述) |
+--------------------------------------------------------------+
v
+--------------------------------------------------------------+
| Backend Lowering (LLVM / VMVX / Vulkan / Metal) |
+--------------------------------------------------------------+
|
LLVM Backend Scheduling (List Scheduling)IREE Linalg 调度层详细图
+--------------------------------------------------------------+
| Linalg-on-tensors IR |
+--------------------------------------------------------------+
|
v
+--------------------------------------------------------------+
| Tiling Pipeline (Rule-based) |
+--------------------------------------------------------------+
| - linalg-tile (决定 tile 大小) |
| - tile-and-fuse（融合 producer-consumer） |
| - vectorization（自动矢量化） |
| - loop unroll |
| - bufferization（分配到 SRAM/stack） |
+--------------------------------------------------------------+
|
v
+--------------------------------------------------------------+
| LLVM Dialect (LLVM IR) |
+--------------------------------------------------------------+
|
LLVM MachineScheduler (List Scheduling)重点：
IREE 的调度高度依赖 Linalg → Tiling Pipeline，没有搜索算法。
最关键对比：TVM vs IREE 调度节点
下图展示两者调度发生的具体位置差异：
TVM: IREE:
Relay StableHLO
| |
v v
TIR (调度核心) Linalg (调度核心)
| - 手写 schedule | - Tile-and-fuse
| - AutoTVM | - Vectorization
| - AutoScheduler | - Rule-based Tiling
v v
PrimFunc LLVM IR
| |
v v
Target (LLVM/CUDA) Target (LLVM/Vulkan)
|
v
LLVM MachineScheduler LLVM MachineSchedulerTVM 调度核心在 TIR 。
IREE 调度核心在 Linalg（MLIR Dialect）。