Vivado FPGA输入时钟约束

##============================= 40mhz时钟输入 ========================

set_property PACKAGE_PIN F17 [get_ports f_clk40mhz]

set_property IOSTANDARD LVCMOS33 [get_ports f_clk40mhz]

create_clock -period 25.000 -name f_clk40mhz -waveform {0.000 12.500} [get_ports f_clk40mhz]

前两行是引脚约束，后一行是时序约束。