论文地址：https://chinaxiv.org/abs/202609.00031
机器翻译+手工整理如下。手工整理的主要工作是把中文和英文按照章节的粒度进行混合，中文在前，英文在后，英文的段落整理，PDF文档Ctrl+CV出来是带有段落内换行的，经过整理后段落内没有换行，和中文段落保持一致，形成适合于网络浏览器查看的格式。此外，文字部分对部分关键字进行了加粗标红便于了解关键技术点。
# 华为的Tau芯片本该融化？ Huawei's τ Chip Was Supposed to Melt?
**作者：Tingbo He**
## 摘要 Abstract
热量是Tau缩放定律最尖锐的质疑------Tau缩放定律是华为折叠硅背后的时间缩放原理，以其致力于缩减的延迟Tau（"韬"）命名。我们的麒麟测量结果将这一质疑彻底颠覆。原因其实每个通勤族都懂：在芯片上，如同在一个工作日中，消耗大部分能量的是路途，而不是办公桌前的工作。
Heat is the sharpest concern on τ scaling law --- the time-scaling principle behind Huawei's folded silicon, named for the delay τ ("Tao") it sets out to shrink. Our Kirin measurements turned that objection upside down. The reason is one every commuter already knows: on a chip, as in a workday, it is the travel that burns the majority of the energy, not the work at the desk.
**关键词：** 逻辑折叠，Tau缩放定律，3D集成，混合键合，低功耗设计，系统技术协同优化。
**Index Terms:**LogicFolding, τ scaling law, 3D integration, hybrid bonding, low-power design, system-technology co-optimization.
## 引言
问一百位芯片工程师，对行业未来最重要的技术是什么，很多人会回答：3D集成------在芯片上堆叠芯片，以增加可用于系统的硅量。问任何一位有经验的芯片工程师，什么会毁掉3D集成，你几乎总会听到同一个词：热量。
这个推理听起来像自然法则。把有源晶体管叠在有源晶体管之上，在每平方毫米里塞进更多东西，把整个东西密封在紧凑的移动设备里，结果似乎不可避免。功率变成热量。困在有限空间里的热量升高温度。温度超过极限就会降频、降低可靠性，最终烧毁芯片。照此逻辑，折叠得越密，烧得越热------折叠得越狠，越快撞墙。
华为等不及这场争论自己平息。被剥夺了让竞争对手继续缩小晶体管的工具后，公司必须打破这个循环------而且要比任何人都早。于是它停止了空间缩放（晶体管的线性尺寸），开始缩放时间：信号穿越芯片关键路径所需的特征延迟。这个延迟写作Tau------发音为tau，中文写作"韬"，Tau缩放定律就是一代又一代压低Tau的行动1。其压缩延迟的旗舰技术叫做LogicFolding（逻辑折叠）：把原本铺展在平面上的电路折叠成垂直堆叠的层级，用微小的垂直连接桥接，让信号走更短的距离。
从一开始，Tau就被构想为电子系统的定律，而非器件技巧：时间可以在每一个层级被压缩------器件、电路、芯片和系统。逻辑折叠是该框架内的一项技术，工作在电路和芯片层级。这个区别很重要，因为行业总在忘记它。晶体管问世不久，就出现了同等重要的发明------集成电路。然而半导体的进步仍被讲述为更好晶体管的故事，仿佛由数十亿晶体管集成的电路只是事后补充。Tau缩放继承了这个盲点：看到Tau芯片里还是那些晶体管，怀疑者就断定没有什么根本改变。接下来的证据将说明他们为何错了。
当逻辑折叠于2026年5月在IEEE国际电路与系统研讨会上首次公开展示时，会场里的质疑浓得化不开。最尖锐的反对直指热量、热量，还是热量。
这个逻辑只有一个问题。对真实硅片------本月即将出货的麒麟2026------的测量显示了相反的结果。该芯片比前代更凉，同时每平方毫米晶体管数量增加了55%，在某些关键任务上功耗降低多达66%。接下来将解释为何如此，以及为何逻辑折叠和Tau缩放定律将带领华为------可能还有其他公司------走向长远的未来。
Ask a hundred chip engineers what the most important technology is to the future of the industry and many will answer: 3D integration --- stacking dies on dies to boost the amount of silicon you can devote to a system. Ask any experienced chip engineer what will kill 3D integration, and you will almost always hear the same word: heat.
The reasoning feels like a law of nature. Stack active transistors on top of active transistors, cram more into every square millimeter, seal the whole thing inside a compact mobile device, and the outcome seems inevitable. Power turns into heat. Heat trapped in a confined space raises temperature. Temperature past a limit throttles the clock, degrades reliability, and eventually cooks the chip. By this logic, the denser you fold, the hotter you burn --- and the harder you fold, the faster you hit the wall.
Huawei cannot wait for that argument to settle itself. Cut off from the tools that let its competitors keep shrinking transistors, the company had to break the cycle --- and break it sooner than anyone else. So it stopped scaling space, the linear dimensions of a transistor, and started scaling time: the characteristic delay a signal takes to travel a chip's
critical paths. That delay is written as τ --- pronounced tau, and rendered in Chinese as Tao (韬), and τ scaling law is a campaign to drive τ down generation after generation 1. Its flagship technique for compressing that delay is called LogicFolding: taking a circuit that used to sprawl across a flat plane and folding it into vertically stacked tiers bridged by tiny vertical links so that signals travel shorter distances.
From the start, τ was conceived as a law of electronic systems rather than a device trick: time can be compressed at every level --- device, circuit, chip, and system. LogicFolding is one technique within that framework, working at the circuit and chip levels. The distinction matters, because the industry keeps forgetting it. Soon after the transistor came an invention of equal consequence --- the integrated circuit. Yet semiconductor progress is still told as a story about better transistors, as if the circuits integrated from billions of transistors were an afterthought. τ scaling inherits that blind spot: seeing the same transistors inside a τ chip, skeptics conclude that nothing fundamental has changed. The evidence that follows shows why they are wrong.
When LogicFolding was first shown in public --- in May 2026, at the IEEE International Symposium on Circuits and Systems --- the skepticism in the room was thick. The single sharpest objection pointed toward heat, heat, and more heat.
There is just one problem with that logic. Measurements on real silicon --- the Kirin 2026, set to ship this month --- showed the opposite. The chip was cooler than its predecessor while comprising 55% more transistors per square millimeter and delivering as much as 66% power reduction on some key tasks. What follows is why that's the case and why LogicFolding and τ scaling law will carry Huawei --- and probably others --- well into the future.
## I. 什么是逻辑折叠？ WHAT IS LOGICFOLDING?
摩尔定律承载计算行业和许多其他行业走了很远，但它一直依赖一个单一技巧：几何缩放23。把晶体管做小，芯片就同时变得更快、更省电。十多年前，这个技巧开始失效。晶体管结构的巧妙改良又买来了十年，但如今每家芯片制造商在每个新节点上都付出更多、得到更少4-7。
对华为来说，这种挤压来得更早、更狠。缩小到行业所称的7纳米节点以下需要极紫外（EUV）光刻，而这无法获得。必须另辟蹊径。
六年的探索带来了对几何缩放的重新审视：它从来只是手段，而非目的。缩小晶体管的意义从来不是小本身，而是小所带来的东西------更快的开关、更短的响应时间、更高的时钟频率。简而言之，逻辑折叠是一种不缩小空间而购买时间的方式。在大致相同的硅面积内，它塞入更多晶体管，并让由它们构建的系统跑得更快。
使能工艺叫做3D混合键合，它更接近焊接而非封装。两片晶圆------或一片晶圆和一颗芯片------被仔细对准、压合在一起，然后缓慢加热。在退火过程中，两个氧化物表面之间形成共价键，融合为单一介质层，同时每面的铜焊盘相向膨胀并熔合为连续金属。结果是堆叠芯片之间一片垂直连接的森林。在当今一些最先进的商用逻辑芯片中，这些连接间距约为10微米，即每100平方毫米不到100万个垂直连接。
真正的设计问题是：每单位面积需要多少垂直连接，折叠才能真正削减RC------即拖慢并消耗每个信号的电阻和电容。没有闭式答案，但有一个直觉是可靠的。典型逻辑工艺的顶层金属间距为720纳米。让键合间距匹配这个数值，面对面晶圆就可以直接连接顶层金属信号。选择更稀疏的间距，这些信号就必须扇出到更稀疏的焊盘------增加走线、拥塞和RC，而这正是折叠要消除的成本。设计空间探索证实了这一直觉：1.5微米已能支持良好的逻辑折叠，1微米更好，720纳米将进一步扩大收益。未来，我们预计将进一步缩小键合间距至480纳米，使混合键合焊盘可以连接到更低金属层，为逻辑折叠提供更多设计自由度。
**我们将混合键合视为晶圆级、跨层的器件步骤，而非封装步骤。**芯片到晶圆键合是一种芯片处理工艺------拾放------源自芯片封装厂。其精度基线很低，即使经过多年收紧仍停留在微米级。晶圆到晶圆键合则从另一个世界起步：晶圆厂处理，光刻工具已将套刻精度控制在几纳米。这个高精度基线是正确的起点，但键合仍需解决光刻扫描机从未面对的问题------应力控制、CMP平坦化、清洗、晶圆翘曲、边缘渐变和对准------才能实现亚微米间距。在40纳米工艺上，我们在麒麟2026中达到了1.5微米混合键合间距------5000万个垂直互连，其中10%到15%承载信号。麒麟2027硅片已达到1微米和超过1亿个垂直互连。三年内，我们预计将匹配720纳米顶层金属间距，实现一对一的齿轮比，垂直互连超过2亿个。
**垂直连接就位后，折叠就可以开始了。**华为的工程师检查了麒麟SoC中最辛苦的模块------NPU、CPU、GPU和DSP------找出每个模块内部最长、最慢、最耗电的水平走线。然后每个模块被重新设计为同时占据两层硅，将那些长水平连接变成从一个芯片到另一个芯片的短垂直跳跃。
在麒麟2026------首款依赖逻辑折叠的移动系统级芯片（SoC）------上，晶体管密度在一代之内从每平方毫米约1.55亿升至2.38亿------跃升55%。这相当于我们过去三年用几何缩小取得的增量。
当然是个好结果，但直觉说功率密度应该同步攀升。
它下降了。
**与平面前代相比，在等性能下，麒麟2026在实际基准测试中实现了NPU 66%、GPU 58%、CPU性能核41%的功耗降低。**我们在每平方毫米里塞入了多得多的晶体管，而芯片每单位工作量运行得更凉，而非更热。
**这个结果值得一个解释，因为它看起来违反了怀疑者所援引的物理学。它没有。**它是一堂关于芯片功率实际去向的课------而答案不在大多数人以为的地方。
Moore's Law has carried the computing industry, and many others, a very long way, but it has always leaned on a single trick: geometric scaling 2, 3. Make the transistor smaller, and chips get faster and thriftier at once. More than a decade ago the trick began to wear out. Clever changes to the transistor's structure bought another decade, but every chipmaker now pays more and gets less with each new node 4--7.
For Huawei, the squeeze came earlier and harder. Shrinking past what the industry calls the 7-nanometer node requires extreme ultraviolet (EUV) lithography, which cannot be accessed. Another way had to be found.
Six years of exploration led to a reappraisal of geometric scaling for what it always was: a means, not an end. The point of shrinking transistors was never smallness itself but the things smallness delivered --- faster switching, shorter response times, higher clock frequencies. In short, LogicFolding is a way of buying time without shrinking space. Within roughly the same silicon area, it packs in more transistors and lets the systems built from them run faster.
The enabling craft is called 3D hybrid bonding, and it is closer to welding than to packaging. Two wafers --- or a wafer and a chip --- are carefully aligned, pressed together, and slowly heated. During the anneal, covalent bonds form across the two oxide surfaces, merging into a single dielectric layer, while the copper pads on each face expand toward each other and fuse into continuous metal. The result is a forest of vertical connections between the stacked dies. In some of the most advanced commercial logic chips today, those connections sit about 10 µm apart, or fewer than 1 million vertical links per 100 mm2.
The real design question is how many vertical connections there are per unit area before folding actually cuts RC --- the resistance and capacitance that slow and tax every signal. There is no closed-form answer, but one piece of intuition is reliable. A typical logic process has a top-metal pitch of 720 nm. Match the bonding pitch to that figure, and face-to-face wafers can join top-metal signals directly. Choose a sparser pitch, and those signals must fan out to sparser pads --- adding wire, congestion, and RC, the very costs folding is meant to remove. Design space exploration confirmed the intuition: 1.5 µm already supports good LogicFolding, 1 µm is better, and 720 nm would expand the benefit further still. In the future, we expect to shrink the bonding pitch further, to 480 nm, so hybrid-bonding pads can connect to lower metal layers and give LogicFolding more design freedom.
We treat the hybrid bonding as a wafer-level, cross-layer device step rather than a packaging step. Die-to-wafer bonding is a die-handling process --- pick and place --- evolved from the chip-packaging factory. Its accuracy baseline is low, and even after years of tightening it still sits at the micrometer level. Wafer-to-wafer bonding starts from a different world: wafer-fab handling, where lithography tools already hold overlay to few nanometers. That high-accuracy baseline is the right starting point, but bonding still has to solve problems the litho scanner never faced --- stress control, CMP planarization, cleaning, wafer bow, edge taper, and alignment --- before it can deliver sub-micrometer pitch. On 40-nm tooling we reached a 1.5 µm hybrid-bonding pitch in Kirin 2026 --- 50 million vertical interconnects, of which 10 to 15 percent carry signals. Kirin 2027 silicon is already at 1 µm and more than 100 million vertical interconnects. Within three years we expect to match the 720 nm top-metal pitch, a one-to-one gear ratio, and more than 200 million vertical interconnects.
With the vertical links in place, the folding could begin. Huawei's engineers examined the hardest-working blocks of the Kirin SoC --- the NPU, the CPU, the GPU and the DSP --- and sought out the longest, slowest, most power hungry horizontal routes inside each one. Each block was then redesigned to occupy two tiers of silicon at once, turning those long, horizontal connections into short vertical hops from one die to another.
On Kirin 2026, the first mobile system-on-chip (SoC) relying on LogicFolding, transistor density rose in a single generation from roughly 155 to 238 million transistors per square millimeter --- a 55% jump. That's an equivalent increase to what we achieved in the previous three years using geometric shrinking.
A great result of course, but intuition says the power density should have climbed in lockstep.
It fell.
Compared to the planar predecessor, at matched performance, Kirin 2026 achieves power reduction of 66% on the NPU, 58% on the GPU, and 41% on the CPU performance core at the real-world benchmark test. We put substantially more transistors into every square millimeter, and the chip ran cooler per unit of work, not hotter.
That result deserves an explanation, because it looks like a violation of the very physics the skeptics invoked. It is not. It is a lesson about where a chip's power actually goes --- and the answer is not where most people assume.
## II. 两份电费账单的故事 A TALE OF TWO POWER BILLS
在智能手机典型的日常工作负载中，芯片以两种方式消耗功率。一种是静态漏电，即即使没有计算时也损失的功率，微乎其微。与之相对的动态功率，即计算过程中损失的功率，约占总电费的90%。
数字电路本质上以两种方式消耗动态能量。第一种是开关：翻转晶体管栅极，对逻辑门的微小电容充放电以将一个位从0变为1再变回来。这是"真正的工作"------计算本身。
第二种是移动信号：对承载这些位从芯片一处到另一处的长金属线充放电。一根导线就是一个铺展在距离上的电容。信号走得越远，充电的电容越多，能量随该电容缩放。在动态功率的教科书表达式中：
**P = α · C · V² · f** (1)
其中C（电容）项并非由晶体管主导。在先进节点上，它由导线主导。互连电容，而非栅极电容，才是能量的去向。
这里就是直觉出错的地方：在现代SoC模块中，导线------移动------通常比栅极------计算------消耗更多能量。处理器把大部分功率花在通勤上，而非思考上。
In a smartphone's typical daily workload, its chips expend power in two ways. One, static leakage, or the power lost even when no computing is happening, is minimal. Its opposite, dynamic power, what's lost during computing, makes up roughly 90% of the total power bill.
Digital circuits essentially consume dynamic energy in two ways. The first is switching: flipping a transistor gate, charging and discharging the tiny capacitance of a logic gate to change a bit from 0 to 1 and back. This is the"real work" --- the computation itself.
The second is moving signals: charging and discharging the long metal wires that carry those bits from one part of the chip to another.A wire is a capacitor smeared out over distance. The farther a signal travels, the more capacitance you charge, and the energy scales with that capacitance. In the textbook expression for dynamic power,
P = α · C · V ^2 · f (1)
the term C (capacitance) is not dominated by the transistors. On an advanced node, it is dominated by wires. Interconnect capacitance, not gate capacitance, is where the energy goes.
Here is what trips up the intuition: in a modern SoC block, the wires --- the moving --- routinely consume more energy than the gates --- the computing. The processor spends most of its power not thinking but commuting.
## III. 你的通勤如何解释你的芯片 HOW YOUR COMMUTE EXPLAINS YOUR CHIP
想想一个普通上班族的每日能量预算。很容易假设大部分花在实际工作上------会议、电子表格、思考。**不是的。****对许多上班族来说，一天中最大的能量支出是通勤：每天两次、在家和办公室之间的开车或坐地铁。**办公桌工作相对便宜；交通占主导。
芯片没什么不同。栅极做思考，导线做通勤。在大型AI集群中同样如此：超过80%的能量花在移动数据上，而非计算数据。同样的失衡，以较温和的形式，存在于每一颗智能手机SoC之中。
一旦你这样看待功率，对折叠的热学质疑就反转了。批评者假设把晶体管塞得更近必然提高功率密度，因为他们隐含地专注于数栅极------办公桌工作。但主导项是通勤。而逻辑折叠做了什么？它把每个人的家搬到离办公室更近的地方。
当你把电路折叠成由亚微米间距混合键合焊盘连接的垂直层级时，曾经穿越长水平导线（数百微米）的信号现在直接向下穿过几微米外的键合焊盘。根据我们的经验，折叠路径上的导线长度在典型核心上缩短20%，在某些关键路径上缩短多达70%。时钟网络------最繁忙、最耗电的导线之一------缩小得如此之多，以至于我们将时钟缓冲器数量削减了一半以上。仅在一个处理模块上，折叠将时钟走线缩短了28%，缓冲器数量从43,600降至19,000。
每根缩短的导线都是更小的待充电电容，因此功率方程中的主导项崩塌了。办公桌工作------实际开关------基本不变，但通勤被大幅削减。这就是功率密度降低的来源。不是因为计算得更少，而是因为移动数据更少。
Consider an average office worker's daily energy budget. It is tempting to assume most of it is spent on the actual job --- the meetings, the spreadsheets, the thinking. **It isn't. For many office workers, the largest energy expenditure of the day is the commute: the drive or the train ride between home and office, twice a day, every day.**Desk work is comparatively cheap; transport dominates.
A chip is no different. The gates do the thinking and the wires do the commuting. It is just as true in a large AI cluster: more than 80% of the energy is spent moving data, not computing on it. The same imbalance, in milder form, lives inside every smartphone SoC.
Once you see power this way, the thermal objection to folding inverts. Critics assumed packing transistors closer must raise power density, because they implicitly focused on counting gates --- the desk work. But the dominant term is the commute. And what does LogicFolding do? It moves everyone's home closer to the office.
When you fold a circuit into vertical tiers connected by hybrid bonding pads at sub-micrometer pitch, signals that once crossed long horizontal wires (hundreds of micrometers) now drop straight down through a bonding pad a few micrometers away. In our experience, wire lengths on folded paths fall by 20% on typical cores and by up to 70% on some critical paths. Clock networks --- some of the busiest, most power-hungry wires --- shrank so much that we cut clock-buffer count by more than half. On one processing block alone, folding shortened the clock
wiring by 28%, and dropped the buffer count from 43,600 to 19,000 .
Every shortened wire is a smaller capacitance to charge, so the dominant term in the power equation collapses. The desk work --- the actual switching --- is essentially unchanged, but the commute has been slashed. That is where the power-density reduction comes from. Not from computing less, but from moving data less.
## IV. 麒麟2026功耗，逐模块拆解 KIRIN 2026 POWER CONSUMPTION, BLOCK BY BLOCK
主导智能手机SoC热预算的模块恰恰是那些移动最多数据的模块：运行AI推理的NPU、渲染像素的GPU、处理信号的DSP。它们发热的原因相同：通信密集型。因为它们在内存、缓冲区和运算单元之间穿梭海量数据，其功率的很大一部分是通勤，而非计算------而这正是折叠攻击的那部分。
为展示每个模块从逻辑折叠中获益多少，我们通过将折叠芯片与其平面前代麒麟9030 Pro在等性能下对比进行测量：相同的AI吞吐量、帧率或基准分数。一个需要更少速度来完成相同工作的模块可以在更低电压下运行，节省会复利增长。同时，由于同样的硅也可以全速运行，每个模块都以两种模式报告：匹配前代，以及全速。以下是硅片报告的各模块数据。
如图1所示，每张图有五个面板------性能、频率、电压、归一化功率和归一化功率密度------以及三根柱：平面麒麟9030 Pro、等性能下的麒麟2026、以及涡轮增压模式下的麒麟2026。归一化面板上的虚线标记9030 Pro基线。折叠面积是两层堆叠的投影面积------即功率密度所依据的面积。
NPU是批评者最担心堆叠的模块，因为它既是最密集的，也是最热的之一。然而它公布了所有模块中最大的降幅：在相同的29 TOPS下，其时钟频率可下调63%，电压可从0.85V降至0.55V。这带来66%的功耗降低，以及惊人的73%功率密度下降。GPU紧随其后：以与麒麟9030 Pro相同的61 FPS运行，但电压低200mV，功耗下降58%。梯度恰好沿着通勤方向：一个模块越并行、越数据饥渴，折叠给它的回报就越多。
DSP是个例外，它教给我们重要一课：有了逻辑折叠，面积可以比功率缩小得更快（图2）。第一代折叠（麒麟2026）以少25%的功耗完成相同工作，但功率密度------每平方毫米的消耗------上升了24%，而真正关系到控热的正是功率密度。上升的原因很直接：折叠将DSP的面积缩小了40%，所以即使功耗下降，其功率密度仍攀升。第二代折叠（麒麟2027）解决了这个问题：我们已经有了那颗硅片，测量到比平面原版更低的功率密度，同时功耗下降47%。换言之，密度是设计输出，而非宿命。
CPU性能核从折叠中获益颇丰------以低9%的时钟和少200mV的供电电压匹配前代基准分数，在HNX基准测试中功耗降低41%。但其功率密度节省在发热模块中最不显著。这不是折叠的失败；这是我们稍后要谈的某件重要事情的线索。
当然，我们不只关心功耗节省。我们还让麒麟2026各模块全速运行，看它们相比9030 Pro能做什么。全速运行时，折叠NPU交付70 TOPS------比前代多141%，GPU多42%帧率，CPU在HNX基准分数上提升18%；在这些模式下它们的功率密度升至平面前代芯片之上。所以折叠给了系统一个平面芯片从未有过的控制旋钮：同一个模块可以是吝啬鬼，也可以是纪录创造者，取决于场景。
The blocks dominating a smartphone SoC's thermal budget are precisely those moving the most data: the NPU running AI inference, the GPU shading pixels, and the DSP crunching signals. These run hot for the same reason: they are communication-intensive. Because they shuttle enormous volumes of data between memory, buffers, and arithmetic units, a large fraction of their power is commute, not compute --- and that is exactly the fraction that folding attacks.
To show how much each block gained from LogicFolding, we measured it by running the folded chip against its planar predecessor, the Kirin9030 Pro, at iso-performance: same AI throughput, frame rate, or benchmark score. A block that needs less speed to do the same work can run at a lower voltage, and the savings compound. Meanwhile, as the same silicon can also run flat out, each block is reported in both modes: matched to its predecessor, and at full throttle. Here is what the silicon reported for the blocks.
As shown in Fig.1, each chart has five panes --- performance, frequency, voltage, normalized power, and normalized power density --- and three bars: the planar Kirin9030 Pro, the Kirin 2026 at iso-performance, and the Kirin 2026 in turbo mode. The dashed line on the normalized panes marks the 9030 Pro baseline. Folded footprints are the projected area of the two-tier stack --- the area that power density is measured against.
Fig.1. Performance, frequency, voltage, normalized power, and normalized power density of the planar Kirin9030 Pro (gray), the Kirin 2026 at iso-performance (teal), and the Kirin 2026 in turbo mode (orange). The GPU's heaviest workload is the most intensive rendering frame from a specific game; CPU HNX bench comprises key mobile application slices, measuring real-world CPU performance and power; Geekbench 6 is an industry-standard CPU performance benchmark. HNX focuses on the real-world user experience, whereas Geekbench 6 targets the heaviest performance workloads.
Fig.2. Normalized footprint, frequency, voltage, normalized power, and normalized power density of the planar Kirin9030 Pro (gray), the Kirin2026 at iso-performance (teal), and the Kirin 2027 at iso-performance (green).
The NPU is the block critics most fear stacking because it is both the densest and among the hottest. Yet it posts the largest reduction of all: at the same 29 TOPS, its clock frequency could be dialed down by 63% and its voltage could be reduced from 0.85 V to 0.55 V. That leads to a reduction in power of 66%, and a decline in power density of a staggering 73%. The GPU is close behind: operating at the same 61 FPS as Kirin9030 Pro but at a voltage that's 200 mV lower, power fell by 58%. The gradient runs exactly along the commute: the more parallel and data-hungry a block, the more folding pays it back.
The DSP is the exception, and it teaches an important lesson: with LogicFolding, area can shrink faster than power (Fig. 2). The first-generation fold (Kirin 2026) does the same work with 25% less power, but power density --- what's consumed per square millimeter --- rose 24%, and it is power density that really matters to controlling heat. The reason for the increase is straightforward: folding shrank the DSP's footprint by 40%, so its power density climbed even as its power consumption fell. The second-generation fold (Kirin 2027) settled the matter: we already have that silicon and have measured a lower power density than the planar original along with a 47% drop in power consumption. Density, in other words, is a design output, not a fate.
The CPU performance core gains handsomely from folding --- matching its predecessor's benchmark score at a 9% lower clock and 200 mV less supply voltage, consuming 41% less power on the HNX benchmark test. But its power-density saving is the most modest of the hot blocks. That is not a failure of folding; it is a clue to something important we'll talk about in a moment.
Of course, we aren't only interested in power savings. We also ran the Kirin 2026 blocks flat out to see what they could do compared to the 9030 Pro. Run at full throttle, the folded NPU delivers 70 TOPS --- 141% more than its predecessor, the GPU delivers 42% more frames, and the CPU delivers an 18% boost on the HNX benchmark score; in those modes their power densities rise above the planar predecessor chip's. So folding hands the system a control dial that the planar chip never had: the same block can be a miser or a record-setter depending on the scenario.
## V. 并行理论：电路中的Tau缩放定律，软件中的阿姆达尔定律 PARALLEL THEORIES: τ SCALING LAW IN CIRCUITS, AMDAHL'S LAW IN SOFTWARE
缩短通勤解释了部分功耗节省，但更多来自降低电压，因为 **动态功率与电压的平方成正比。**逻辑折叠通过将电路分为三类来解锁这种降低：真正串行的，需要峰值频率和电压；可并行化的电路，将工作分散到许多并排运行的副本上；以及介于两者之间的电路，部分串行部分并行8。
不折不扣的串行电路是少数。压倒性地，现代SoC的晶体管服务于第二和第三类------NPU、GPU和DSP，它们消耗不成比例的大量功率，恰恰因为它们是宽的、并行的、数据饥渴的。CPU性能核（大核）是第一类最清晰的居民，因为其单一快速整数执行线程无法并行化，必须运行在电压和频率曲线的顶端附近。回想一下，折叠在HNX基准等性能下只为它买到了9%的时钟降低------这是线性的通勤节省，而非完整的二次电压节省。将逻辑折叠应用于低并行度CPU性能核需要精细的设计、先进的EDA工具链和漫长的验证周期。这是系统性的大修，而非权宜之计。虽然麒麟2026已交付了可观的收益，但大部分工作还在前方，需要未来三到五年内激进的、探索性的创新。然而，在通往这些终极收益的道路上，每一年都会实现切实的、复利的改进。
幸运的是，这些架构障碍不必仅靠硅来克服。智能手机有一个天真分析会忽略的东西：深度的软硬件协同设计。与其强迫一个英勇的大核承担每一个苛刻的工作负载，任务调度器和折叠布局被协同优化，以在软件中并行化任务并将它们分派到多个小而高效的核心上。这使大核必须拥有的工作串行部分保持在应用允许的最小程度。这将工作负载从第一类转移到第二类，在那里二次电压杠杆生效。
在这里，两个杠杆结合了。折叠缩短导线，同时在相同面积内为更多晶体管腾出空间。那些额外的晶体管可以用来创建许多电路副本，然后并行运行，分散工作，使每个都能以更慢的时钟和更低的电压运行。通勤论证在C上买到线性节省，而并行论证在V²上买到二次节省。
折叠NPU是一个绝佳例子。其前代由一个大核和两个能效核组成，而折叠带来的晶体管盈余换来四个大核。更宽的阵列在0.7V下交付70 TOPS------远低于前代需要0.85V才能交付不到一半的水平。更多硬件，运行得更温和，做得更多：二次杠杆，完全如方程所指示的那样运作。
这就是为什么更密集的芯片消耗更少功率。需要高电压的串行工作足够小，不至于主导功率预算；其他一切------庞大的并行多数------被折叠得更宽，时钟更温和，运行在更低电压下。
这种设计映照了吉恩·阿姆达尔的著名洞见：一个程序的串行部分限制了并行性能给你带来多少收益。阿姆达尔定律关乎软件。逻辑折叠揭示的是它的硬件孪生：硅的串行部分很小，所以芯片的大部分可以用速度换取并行性。它们如双星并立------一个治理代码中的算法，另一个治理电路中的延迟和能量，构成系统技术协同优化（STCO）的理论基石。
**Shortening the commute explains some of the power savings, but even more came from reducing voltage, because dynamic power is proportional to the square of voltage.**LogicFolding unlocks this reduction by sorting circuits into three kinds: the truly serial, demanding peak frequency and voltage; the parallelizable circuits, spreading work across many copies running side by side; and those circuits lying in between, partly serial and partly parallel 8.
The uncompromisingly serial circuits are the minority. Overwhelmingly, a modern SoC's transistors serve the second and third categories, the NPU, GPU, and DSP, which draw an outsized amount of power precisely because they are wide, parallel, and data-hungry. The CPU performance core (big core) is the clearest inhabitant of the first category, because its single fast integer thread of execution cannot be parallelized, and it must run near the top of the voltage and frequency curve. Recall that folding buys it only a modest 9% clock reduction at iso-performance on HNX benchmark --- the linear commute saving, not the full quadratic voltage one. Applying LogicFolding to low-parallelism CPU performance core requires meticulous design, advanced EDA toolchains, and long verification cycles. It is a systemic overhaul, not a quick fix. While substantial gains have been delivered in Kirin 2026, the bulk of the work lies ahead, requiring aggressive, exploratory innovation over the next three to five years. Yet, on the path to these ultimate yields, tangible and compounding improvements will be realized every single year.
Fortunately, these architectural hurdles do not have to be overcome by silicon alone. Smartphones have something that a naive analysis misses: deep hardware-software co-design. Rather than forcing one heroic big core to shoulder every demanding workload, task schedulers and folded floorplans are co-optimized to parallelize tasks in software and dispatch them across several small, efficient cores. This keeps the serial fraction of the work that the big core must own as small as the application allows. This shifts workloads from category one to category two, where the quadratic voltage lever applies.
Here, both levers combine. Folding shortens wires while freeing up room for many more transistors within the same footprint. Those extra transistors can be spent creating many copies of circuits which can then be run in parallel, spreading out the work so each can run at slower clock and lower voltage. Where the commute argument buys a linear saving in C, the parallelism argument buys a quadratic saving in V 2.
The folded NPU is a prime example. While its predecessor comprised one big core and two efficiency cores, the transistor surplus from folding paid for four big cores. The wider array delivers 70 TOPS at 0.7 V --- well below the 0.85 V its predecessor needed to deliver less than half that. More hardware, running gentler, doing more: the quadratic lever, working exactly as the equation dictates.
That is why a denser chip drew less power. The serial work requiring high voltage is small enough not to dominate the power budget; everything else --- the vast parallel majority --- is folded wider, clocked gentler, and run at lower voltage.
This design mirrors Gene Amdahl's famous insight: a program's serial fraction limits how much parallelism can buy you. Amdahl's law is about software. What LogicFolding exposes is its hardware twin: the serial fraction of the silicon is small, so most of the chip can trade speed for parallelism. They stand as twin stars --- one governing algorithms in code, the other governing delay and energy in circuit, forming the theoretical bedrock of System-Technology Co-Optimization (STCO).
## VI. 设计消除热点 DESIGNING AWAY HOT SPOTS
尽管我们用逻辑折叠取得了所有这些功耗节省，仍有人可能争辩说我们会有热量问题。堆叠两层忙于开关的晶体管会集中热量，因为底层产生的热量必须穿过顶层材料才能逸出。
我们认为批评者瞄错了指标。重要的不是热量，而是热密度------再深一层，是晶体管的结温，这才是真正支配速度、漏电和可靠性的指标。芯片不是因为耗散一定瓦数而失效，而是当晶体管结温攀升超过其工作温度极限时。每一个值得做的热学论证最终都是关于那个结温的论证。
有两件事让它受控。第一，折叠在源头降低热密度：等性能下总功率确实下降了，降低的功率分布在多个有源硅层而非单一密集平面上。这实现了更低的每立方毫米瓦数，而热密度正是决定结温有多高的东西。
第二，剩余的热量被管理。因为折叠缩小了NPU和其他发热模块的面积，就有空间让热量水平扩散，消除局部热点并降低结温，然后才垂直传向表面。底层比顶层高几度的温和垂直温度梯度，被作为设计参数预算------通过将最热的模块放在热量最容易逸出的位置。真正的敌人不是平均温度，而是结温远高于邻居的局部热点。当设计工具主动在各层间交错冷热逻辑、防止热点直接堆叠在彼此之上时，折叠就赢得了它的热学余量。
这就是为什么我们的麒麟2026实现刻意保守：仅沿获益最大的关键路径选择性应用折叠，采用热感知布局而非盲目堆叠一切。这样做------降低热密度、水平扩散、预算垂直梯度、排查热点------结温就保持在其窗口之内。
Despite all the power savings we've accomplished with LogicFolding, one could still argue that we'll have a heat problem. Stacking two tiers of busily-switching transistors concentrates heat, because what's generated at the bottom tier must move through material of the top tier to escape.
We contend that critics are aiming at the wrong metric. What matters is not the heat, but the heat density --- and, one level deeper, the junction temperature of transistors, which is the metric that actually governs speed, leakage, and reliability. A chip fails not from dissipating a certain number of watts, but when a transistor junction climbs past its operating temperature limit. Every thermal argument worth making is ultimately an argument about that junction temperature.
Two things keep it in control. First, folding lowers heat density at the source: total power genuinely dropped at iso-performance and the reduced power is distributed across multiple active silicon tiers rather than a single densely populated plane. This achieves lower watts-per-cubic-millimeter, and heat density is the thing that sets how hot a junction gets.
Second, the remaining heat is managed. Because folding shrinks the footprint of the NPU and other hot blocks, there is room to allow the heat to spread out horizontally, eliminating localized hotspots and reducing junction temperatures, before it travels vertically to the surface. The modest vertical temperature gradient where the bottom tier runs a few degrees warmer than the top, is budgeted as a design parameter by placing the hottest blocks where heat escapes most easily. The genuine enemy is not average temperature, but the localized hotspot where junction temperature spikes far above its neighbors. Folding earns its thermal headroom when the design tools actively interleave hot and cool logic across tiers, preventing hotspots from stacking directly atop one another.
That is why our Kirin 2026 implementation was deliberately conservative: folding applied selectively along the critical paths that gain most, with thermal-aware placement rather than blindly stacking everything. Done that way --- lowering heat density, spreading horizontally, budgeting vertical gradients, and hunting down hotspots --- the junction temperature stays inside its window.
## VII. 西西弗斯，但山通向某处 SISYPHUS , BUT THE HILL LEADS SOMEWHERE
以最终胜利的调子结尾是不诚实的。
Tau是时间缩放定律，不是能量定律。一个折叠系统跑得更快但烧更多电，并不违反任何时间缩放原则------但它会在午饭前耗尽你的电池。运行凉爽的麒麟之所以出现，是因为我们刻意将折叠的时间余量花在了更低的电压和功率上。这种交换是一门配套的纪律，不是定律的免费后果。
以三分之一功耗完成前代工作的折叠NPU，也能以141%的速度超越前代，超过其功率密度。物理学允许两种设置；纪律选择凉爽的那个。这是我们计划在每一代新芯片中做出的选择。
折叠CPU刻意保守，仅针对关键路径。然而，它今年已将性能核频率恢复到3.1GHz。在未来三到五年内释放逻辑折叠的全部潜力需要激进的、全行业的创新------扩展设计空间、缩小混合键合间距、集成更低金属层TSV、垂直堆叠更多层级，等等。逻辑折叠将为麒麟CPU核心频率达到5GHz及更高铺平道路。该路线图是可行的，且在经济上可持续。
在神话中，西西弗斯被判将巨石推上山，却只能看着它滚下来，重新开始。Tau缩放下的工程共享这种节奏：折叠芯片，赚得时间余量，花在功率上------然后下一代到来，巨石重新开始。上述提出的折叠走线不是对那个循环的逃避；它是下一次推动。我们的故事与神话分道扬镳之处在于，这座山通向某处：每个循环都留下一颗计算更多、燃烧更少的芯片，而累积的距离就是行业所称的进步。工作永远不会完成------那不是定律的弱点，那是职位描述。而必须想象工程师们是快乐的。
It would be dishonest to end on a note of final victory.
τ is a time scaling law, not an energy law. A folded system running faster but burning more power violates no time-scaling principle --- yet it would drain your battery by lunchtime. The cool-running Kirin happened because we deliberately spent the time headroom of folding on lower voltage and power. That trade is a companion discipline, not a free consequence of the law.
The folded NPU doing its predecessor's work on a third of the power can also outrun that predecessor by 141%, exceeding its power density. Physics permits both settings; discipline chooses the cool one. It's a choice we plan to make with each new generation of chips.
The folded CPU is deliberately conservative, targeting only critical paths. Yet, it already restores performance core frequencies to 3.1 GHz this year. Unlocking the full potential of LogicFolding over the next three to five years requires aggressive, industry-wide innovation --- expanding the design space, shrinking hybrid bonding pitch, integrating lower-metal TSVs, vertically stacking more tiers, et al. LogicFolding will pave the way for Kirin CPU core frequency to reach 5 GHz and beyond. The roadmap is feasible and economically viable.
In the myth, Sisyphus is condemned to push his boulder up the hill, only to watch it roll down and start over. Engineering under τ scaling law shares this rhythm: fold the chip, earn the time headroom, spend it on power --- then the next generation arrives and the boulder starts over. The above proposed folded wiring is not an escape from that cycle; it is the next push. Where our story parts ways with the myth is that this hill leads somewhere: every cycle leaves behind a chip that computes more and burns less, and the accumulated distance is what the industry calls progress. The work is never finished --- that is not the law's weakness, it is the job description. And one must imagine the engineers happy.
## VIII. 凉爽才是前进方向 COOLER IS THE WAY FORWARD
但热量------每个人第一个伸手去抓的反对理由------结果建立在对芯片能量去向的误解之上。恐惧数的是办公桌工作。物理学被通勤主导。逻辑折叠缩短通勤，一举降低时间常数Tau和能量，因为距离同时耗费两者。
我们能看到的Tau的每一个未来，都在功率上定胜负。时间余量是工具；能量是奖品。这个定律未来十年将被评判的，不是折叠堆叠跑得多快，而是它们运行时烧得多少。
本该融化的Tau芯片反而跑得更凉------不是尽管折叠，而是因为折叠。Tau（韬），归根结底，在不止一个方向上切割。
But heat --- the objection everyone reaches for first --- turns out to rest on a misunderstanding of where a chip spends energy. The fear counts the desk work. The physics is dominated by the commute. LogicFolding shortens the commute, lowering time constant τ and energy in one stroke, because distance costs both.
Every future we can see for τ is won or lost on power. Time headroom is the instrument; energy is the prize. The next decade of this law will be judged not by how fast the folded stacks run but by how little they burn while running.
The τ chip that was supposed to melt ran cooler instead --- not in spite of the folding, but because of it. τ (Tao), in the end, cuts in more directions than one.
--
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