Lfsr5

A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be "maximum-length". A maximum-length LFSR of n bits cycles through 2n-1 states before repeating (the all-zero state is never reached).

The following diagram shows a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. (Tap positions are usually numbered starting from 1). Note that I drew the XOR gate at position 5 for consistency, but one of the XOR gate inputs is 0.

复制代码
module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 

    
    always@ (posedge clk)
        if(reset)
            q <= 5'h1;
    	else begin
            q[0] <= q[1];
            q[1] <= q[2];
            q[2] <= q[0] ^ q[3];
            q[3] <= q[4];
            q[4] <= 0 ^ q[0];
        end
endmodule
相关推荐
迎风打盹儿2 天前
FPGA同步复位、异步复位、异步复位同步释放仿真
verilog·fpga·vivado·复位
肯德基疯狂星期四-V我503 天前
【FPGA】状态机思想实现LED流水灯&HDLbits组合逻辑题训练
fpga开发·verilog·de2-115
可编程芯片开发4 天前
基于FPGA的特定序列检测器verilog实现,包含testbench和开发板硬件测试
fpga开发·verilog·特定序列检测
超级大咸鱼12 天前
verilog实现32位有符号流水乘法器
verilog·乘法器
超级大咸鱼13 天前
verilog实现十进制正数与ASCII码互转
verilog·fpga·ascii
我爱C编程15 天前
基于FPGA的16QAM+帧同步系统verilog开发,包含testbench,高斯信道,误码统计,可设置SNR
fpga开发·verilog·16qam·帧同步·误码统计·高斯信道
早睡身体好~15 天前
FPGA原型验证,从零开始直到入门全过程
fpga开发·verilog·soc
9527华安20 天前
Xilinx系列FPGA视频采集转HDMI2.0输出,基于HDMI 1.4/2.0 Transmitter Subsystem方案,提供6套工程源码和技术支持
fpga开发·verilog·视频采集·hdmi2.0·4k
双料毒狼_s24 天前
【FPGA实战】Verilog实现DE2-115的流水灯控制
fpga开发·verilog
简简单单做算法1 个月前
基于FPGA的图像退化算法verilog实现,分别实现横向和纵向运动模糊,包括tb和MATLAB辅助验证
fpga开发·verilog·图像退化