Lfsr5

A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be "maximum-length". A maximum-length LFSR of n bits cycles through 2n-1 states before repeating (the all-zero state is never reached).

The following diagram shows a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. (Tap positions are usually numbered starting from 1). Note that I drew the XOR gate at position 5 for consistency, but one of the XOR gate inputs is 0.

复制代码
module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 

    
    always@ (posedge clk)
        if(reset)
            q <= 5'h1;
    	else begin
            q[0] <= q[1];
            q[1] <= q[2];
            q[2] <= q[0] ^ q[3];
            q[3] <= q[4];
            q[4] <= 0 ^ q[0];
        end
endmodule
相关推荐
m0_547486666 天前
《数字电路与逻辑设计:基于Verilog HDL和Quartus Prime》全套PPT课件2026
verilog·数字电路·数字逻辑电路
学习FPGA的电气小兴兴7 天前
基于FPGA的CORDIC旋转模式实现sin和cos运算_采用EGo1板卡上板验证【FPGA数字信号处理第5讲】
fpga开发·信号处理·数字信号处理·verilog·cordic·ego1·fpga设计入门与提高
啄缘之间14 天前
1.【SVA】什么是SVA?
经验分享·学习·测试用例·verilog·sva
SDAU200515 天前
verilog计数器中增减操作之资源占用
verilog
学习FPGA的电气小兴兴18 天前
基于FPGA的CORDIC向量模式实现arctan运算,Verilog HDL实现
嵌入式硬件·fpga开发·数字信号处理·verilog·fpga·cordic·arctan
学习FPGA的电气小兴兴24 天前
基于FPGA的CORDIC旋转模式实现sin和cos运算
fpga开发·信号处理·数字信号处理·verilog·fpga·verilog hdl·cordic
FPGA开源工坊1 个月前
ISP图像处理--Bayer Raw格式
图像处理·人工智能·verilog·fpga·isp
qq_150841991 个月前
用verilog语言在Quartus Prime Lite 18中对CPLD EPM570T100C5进行编程
verilog·quartus·cpld
芯路行者2 个月前
4.4 HDLBits —— 更多时序逻辑电路
fpga开发·verilog·fpga·hdlbits
芯路行者2 个月前
7 HDLBits —— 验证:编写测试激励文件
fpga开发·verilog·fpga·hdlbits