Lfsr5

A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be "maximum-length". A maximum-length LFSR of n bits cycles through 2n-1 states before repeating (the all-zero state is never reached).

The following diagram shows a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. (Tap positions are usually numbered starting from 1). Note that I drew the XOR gate at position 5 for consistency, but one of the XOR gate inputs is 0.

复制代码
module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 

    
    always@ (posedge clk)
        if(reset)
            q <= 5'h1;
    	else begin
            q[0] <= q[1];
            q[1] <= q[2];
            q[2] <= q[0] ^ q[3];
            q[3] <= q[4];
            q[4] <= 0 ^ q[0];
        end
endmodule
相关推荐
闻道且行之7 天前
FPGA|Quartus II 中使用TCL文件进行引脚一键分配
fpga开发·verilog·tcl
一丢沙10 天前
Verilog 硬件描述语言自学——重温数电之典型组合逻辑电路
开发语言·算法·fpga开发·verilog
徐晓康的博客17 天前
Verilog功能模块--SPI主机和从机(03)--SPI从机设计思路与代码解析
fpga开发·verilog·主机·spi·从机
微小冷1 个月前
OV5640 相机开发流程
fpga开发·verilog·ov5640·双目相机·相机开发
ChipCamp1 个月前
ChipCamp探索系列 -- 1. Soft-Core RISC-V on FPGA
fpga开发·verilog·risc-v
FPGA小迷弟1 个月前
京微齐力系列FPGA---- Debugware IP核使用教程!!!
物联网·fpga开发·硬件架构·verilog·fpga
月光技术杂谈2 个月前
上海RISC-V峰会-香山开源RISC-V CPU随想随记
verilog·risc-v·chisel·vhdl·香山·开源cpu·xiangshan
可编程芯片开发2 个月前
基于FPGA的多级流水线加法器verilog实现,包含testbench测试文件
fpga开发·verilog·加法器·多级流水线
进击的奶龙2 个月前
02VCS_使用教程
verilog·仿真·eda
热爱学习地派大星2 个月前
Xilinx FPGA功耗评估
fpga开发·verilog·vivado·fpga功耗·xpe